Search results for "ASAP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Brent E. Nelson	The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines.	ASAP	2006	DBLP DOI BibTeX RDF
34	DaeGon Kim, Sanjay V. Rajopadhye	An Improved Systolic Architecture for LU Decomposition.	ASAP	2006	DBLP DOI BibTeX RDF
34	Tung N. Pham, Earl E. Swartzlander Jr.	Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology.	ASAP	2006	DBLP DOI BibTeX RDF
34	Elie H. Sarraf, Messaoud Ahmed Ouameur, Daniel Massicotte	FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System.	ASAP	2006	DBLP DOI BibTeX RDF
34	Youtao Zhang, Jun Yang 0002, Lan Gao	Efficient Group KeyManagement with Tamper-resistant ISA Extensions.	ASAP	2006	DBLP DOI BibTeX RDF
34	Júlio C. B. de Mattos, Stephan Wong, Luigi Carro	The Molen FemtoJava Engine.	ASAP	2006	DBLP DOI BibTeX RDF
34	Ivan D. Castellanos, James E. Stine	A 64-bit Decimal Floating-Point Comparator.	ASAP	2006	DBLP DOI BibTeX RDF
34	Shaoxiong Hua, Pushkin R. Pari, Gang Qu 0001	Dual-Processor Design of Energy Efficient Fault-Tolerant System.	ASAP	2006	DBLP DOI BibTeX RDF
34	Jeffrey M. Arnold	Software Configurable Processors.	ASAP	2006	DBLP DOI BibTeX RDF
34	Herwin Chan, Miguel Griot, Andres I. Vila Casado, Richard D. Wesel, Ingrid Verbauwhede	High Speed Channel Coding Architectures for the Uncoordinated OR Channel.	ASAP	2006	DBLP DOI BibTeX RDF
34	Aasavari Bhave, Eurípides Montagne, Edgar Granados	Describing Quantum Circuits with Systolic Arrays.	ASAP	2006	DBLP DOI BibTeX RDF
34	Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Fabien Coelho	Buffer and register allocation for memory space optimization.	ASAP	2006	DBLP DOI BibTeX RDF
34	Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson	An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets.	ASAP	2006	DBLP DOI BibTeX RDF
34		External Referees.	ASAP	2006	DBLP DOI BibTeX RDF
34	Richard Hughey, Andrea Di Blas	The UCSC Kestrel Application-Unspecific Processor.	ASAP	2006	DBLP DOI BibTeX RDF
34	Sandeep B. Singh, Jayanta Biswas, S. K. Nandy 0001	A Cost Effective Pipelined Divider for Double Precision Floating Point Number.	ASAP	2006	DBLP DOI BibTeX RDF
34	Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula	Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions.	ASAP	2006	DBLP DOI BibTeX RDF
34	Philippe Clauss, Bénédicte Kenmei	Polyhedral Modeling and Analysis of Memory Access Profiles.	ASAP	2006	DBLP DOI BibTeX RDF
34	Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos	An Energy-Delay Efficient Subword Permutation Unit.	ASAP	2006	DBLP DOI BibTeX RDF
34	Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo	2D-VLIW: An Architecture Based on the Geometry of Computation.	ASAP	2006	DBLP DOI BibTeX RDF
34	Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten	Dynamic-SIMD for lens distortion compensation.	ASAP	2006	DBLP DOI BibTeX RDF
34	Antoni Portero, Guillermo Talavera, Marius Monton, Borja Martínez, Francky Catthoor, Jordi Carrabina	Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation.	ASAP	2006	DBLP DOI BibTeX RDF
34	Sebastian Siegel, Renate Merker	Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.	ASAP	2006	DBLP DOI BibTeX RDF
34	Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat	Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards.	ASAP	2006	DBLP DOI BibTeX RDF
34	Paul L. Master	Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing Systems.	ASAP	2006	DBLP DOI BibTeX RDF
34	Thorsten von Sydow, Bernd Neumann, Holger Blume, Tobias G. Noll	Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic.	ASAP	2006	DBLP DOI BibTeX RDF
34	Woo Hyung Lee, Pinaki Mazumder	Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder.	ASAP	2006	DBLP DOI BibTeX RDF
34	Grant Martin	Recent Developments in Configurable and Extensible Processors.	ASAP	2006	DBLP DOI BibTeX RDF
34	Thomas Warsaw, Marcin Lukowiak	Architecture design of an H.264/AVC decoder for real-time FPGA implementation.	ASAP	2006	DBLP DOI BibTeX RDF
34	Antoine Scherrer, Antoine Fraboulet, Tanguy Risset	A Generic Multi-Phase On-Chip Traffic Generation Environment.	ASAP	2006	DBLP DOI BibTeX RDF
34	Daesun Oh, Keshab K. Parhi	Low Complexity Design of High Speed Parallel Decision Feedback Equalizers.	ASAP	2006	DBLP DOI BibTeX RDF
34	Drew Taussig, Andreas Hoffmann 0002, Achim Nohl, Andrea Kroll	Application Specific Processing: A Tools Approach.	ASAP	2006	DBLP DOI BibTeX RDF
34	Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede	Throughput Optimized SHA-1 Architecture Using Unfolding Transformation.	ASAP	2006	DBLP DOI BibTeX RDF
34	Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil	Parameterized Looped Schedules for Compact Representationof Execution Sequences.	ASAP	2006	DBLP DOI BibTeX RDF
34	Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi	NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.	ASAP	2006	DBLP DOI BibTeX RDF
34	Yiyu Tan, Chihang Yau, Anthony S. Fong	Architectural Support on Object-Oriented Programming in a JAVA Processor.	ASAP	2006	DBLP DOI BibTeX RDF
34	Humberto Calderon, Stamatis Vassiliadis	Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit.	ASAP	2006	DBLP DOI BibTeX RDF
34	Mythri Alle, Jayanta Biswas, S. K. Nandy 0001	High Performance VLSI Architecture Design for H.264 CAVLC Decoder.	ASAP	2006	DBLP DOI BibTeX RDF
34	Carl Ebeling	Configurable Computing Platforms - Promises, Promises.	ASAP	2006	DBLP DOI BibTeX RDF
34	Peter R. Cappello	Multicore processors as Array Processors: Research Opportunities.	ASAP	2006	DBLP DOI BibTeX RDF
34		16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece	ASAP	2005	DBLP BibTeX RDF
34	Cor Meenderinck, Sorin Cotofana, Casper Lageweg	High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology.	ASAP	2005	DBLP DOI BibTeX RDF
34	Konrad Walus, Mike Mazur, Gabriel Schulhof, Graham A. Jullien	Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA).	ASAP	2005	DBLP DOI BibTeX RDF
34	Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala	256-State Rate 1/2 Viterbi Decoder on TTA Processor.	ASAP	2005	DBLP DOI BibTeX RDF
34	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform.	ASAP	2005	DBLP DOI BibTeX RDF	SIMD extensions, Discrete Wavelet Transform, lifting scheme
34	M. Van Der Horst, Kees van Berkel 0001, Johan Lukkien, Rudolf H. Mak	Recursive Filtering on a Vector DSP with Linear Speedup.	ASAP	2005	DBLP DOI BibTeX RDF
34	Enrico Ng, Gyungho Lee	Eliminating Sorting in IP Lookup Devices using Partitioned Table.	ASAP	2005	DBLP DOI BibTeX RDF
34	Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata	On-line Multioperand Addition Based on On-line Full Adders.	ASAP	2005	DBLP DOI BibTeX RDF
34	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.	ASAP	2005	DBLP DOI BibTeX RDF
34	Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere	Expression Synthesis in Process Networks generated by LAURA.	ASAP	2005	DBLP DOI BibTeX RDF
34	Andreas Fidjeland, Wayne Luk	Customising Application-Speci.c Multiprocessor Systems: a Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
34	Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal	On the Advantages of Serial Architectures for Low-Power Reliable Computations.	ASAP	2005	DBLP DOI BibTeX RDF
34	Ludovic L'Hours	Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
34	Milos D. Ercegovac, Jean-Michel Muller	Variable Radix Real and Complex Digit-Recurrence Division.	ASAP	2005	DBLP DOI BibTeX RDF
34	Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev	The Midlifekicker Microarchitecture Evaluation Metric.	ASAP	2005	DBLP DOI BibTeX RDF	pipeline, microarchitecture, ILP
34	Jayaprakash Pisharath, Alok N. Choudhary	Design of a Hardware Accelerator for Density Based Clustering Applications.	ASAP	2005	DBLP DOI BibTeX RDF
34	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware.	ASAP	2005	DBLP DOI BibTeX RDF
34	Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon	Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x.	ASAP	2005	DBLP DOI BibTeX RDF
34		External Referees.	ASAP	2005	DBLP DOI BibTeX RDF
34		Copyright Page.	ASAP	2005	DBLP DOI BibTeX RDF
34	Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede	Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2n).	ASAP	2005	DBLP DOI BibTeX RDF	Multiplication in GF(2^n), Systolic array architecture, Montgomery method for point multiplication, Elliptic Curve Cryptography (ECC), Hardware implementation
34	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
34	Alain Darte, Steven Derrien, Tanguy Risset	Hardware/Software Interface for Multi-Dimensional Processor Arrays.	ASAP	2005	DBLP DOI BibTeX RDF
34	Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina	Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.	ASAP	2005	DBLP DOI BibTeX RDF
34	Bharath N, Nagaraju Bussa	Artificial Deadlock Detection in Process Networks for ECLIPSE.	ASAP	2005	DBLP DOI BibTeX RDF
34	Yang Yang 0040, Tong Jing, Xianlong Hong, Yu Hu 0002, Qi Zhu 0002, Xiaodong Hu 0001, Guiying Yan	Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.	ASAP	2005	DBLP DOI BibTeX RDF
34	Amilcar do Carmo Lucas, Rolf Ernst	An Image Processor for Digital Film.	ASAP	2005	DBLP DOI BibTeX RDF	weak-programing, stream-based architechture, digital .lm, recon.gurable, FPGA
34	Jie Han 0001, Erin Taylor 0001, Jianbo Gao, José A. B. Fortes	Faults, Error Bounds and Reliability of Nanoelectronic Circuits.	ASAP	2005	DBLP DOI BibTeX RDF
34	Maria J. Avedillo, José M. Quintana, Héctor Pettenghi	Logic Models Supporting the Design of MOBILE-based RTD Circuits.	ASAP	2005	DBLP DOI BibTeX RDF
34	João M. P. Cardoso	On Estimations for Compiling Software to FPGA-based Systems.	ASAP	2005	DBLP DOI BibTeX RDF
34	Michael T. Frederick, Nathan A. VanderHorn, Arun K. Somani	Real-time H/W Implementation of the Approximate Discrete Radon Transform.	ASAP	2005	DBLP DOI BibTeX RDF
34	Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai	A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering Coprocessor.	ASAP	2005	DBLP DOI BibTeX RDF
34	Jan-Willem van de Waerdt, Stamatis Vassiliadis	Instruction Set Architecture Enhancements for Video Processing.	ASAP	2005	DBLP DOI BibTeX RDF
34		Program Committee.	ASAP	2005	DBLP DOI BibTeX RDF
34	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Square Root Using Newton-Raphson Iteration.	ASAP	2005	DBLP DOI BibTeX RDF
34	Ian Steiner, P. Chan, Laurent Imbert, Graham A. Jullien, Vassil S. Dimitrov, G. H. McGibney	A Fault-Tolerant Modulus Replication Complex FIR Filter.	ASAP	2005	DBLP DOI BibTeX RDF
34	Vida Kianzad, Shuvra S. Bhattacharyya, Gang Qu 0001	CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems.	ASAP	2005	DBLP DOI BibTeX RDF
34	Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka	A Programmable DSP Architecture for Wireless Communication Systems.	ASAP	2005	DBLP DOI BibTeX RDF
34	Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere	Behavioral specification of control interface for signal processing applications.	ASAP	2005	DBLP DOI BibTeX RDF
34	Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis	Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays.	ASAP	2005	DBLP DOI BibTeX RDF
34	Thi Nguyen, Kaijian Shi	Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs.	ASAP	2005	DBLP DOI BibTeX RDF
34	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	Exploring Design Space of VLIW Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
34		Message from the Conference Chairs.	ASAP	2005	DBLP DOI BibTeX RDF
34	Moboluwaji O. Sanu, Earl E. Swartzlander Jr.	Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields.	ASAP	2005	DBLP DOI BibTeX RDF
34		Title Page.	ASAP	2005	DBLP DOI BibTeX RDF
34	Tom R. Jacobs, José L. Núñez-Yáñez	A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor.	ASAP	2005	DBLP DOI BibTeX RDF
34	Michael J. Flynn	Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems.	ASAP	2005	DBLP DOI BibTeX RDF
34	Samarjit Chakraborty	Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing.	ASAP	2005	DBLP DOI BibTeX RDF
34		Conference Organizers.	ASAP	2005	DBLP DOI BibTeX RDF
34	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
34	Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner	Instruction Set Extensions for Reed-Solomon Encoding and Decoding.	ASAP	2005	DBLP DOI BibTeX RDF
34	Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
34	Björn Jäger, Jörg-Christian Niemann, Ulrich Rückert 0001	Analytical approach to massively parallel architectures for nanotechnologies.	ASAP	2005	DBLP DOI BibTeX RDF
34	Adrian Burian, Perttu Salmela, Jarmo Takala	Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture.	ASAP	2005	DBLP DOI BibTeX RDF
34	Kiyofumi Tanaka	Casablanca II: Implementation of a Real-Time RISC.	ASAP	2005	DBLP DOI BibTeX RDF
34	Karim Ben Chehida, Michel Auguin	A SW/Configware Codesign Methodology for Control Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
34	Jean-Luc Beuchat, Jean-Michel Muller	Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement.	ASAP	2005	DBLP DOI BibTeX RDF
34	Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire	Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems.	ASAP	2005	DBLP DOI BibTeX RDF
34	Christian Plessl, Marco Platzner	Zippy - A coarse-grained reconfigurable array with support for hardware virtualization.	ASAP	2005	DBLP DOI BibTeX RDF
34	José L. Núñez-Yáñez, Vassilios A. Chouliaras	Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.	ASAP	2005	DBLP DOI BibTeX RDF