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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 700 occurrences of 376 keywords
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Results
Found 2246 publication records. Showing 2246 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Christian Helm, Soramichi Akiyama, Kenjiro Taura |
Reliable Reverse Engineering of Intel DRAM Addressing Using Performance Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 28th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2020, Nice, France, November 17-19, 2020, pp. 1-8, 2020, IEEE, 978-1-7281-9238-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Onkar Patil, Frank Mueller 0001, Latchesar Ionkov, Jason Lee, Michael Lang 0003 |
Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 28th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2020, Nice, France, November 17-19, 2020, pp. 1-8, 2020, IEEE, 978-1-7281-9238-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Curt Beckmann, Ramkumar Krishnamoorthy, Han Wang 0009, Andre Lam, Changhoon Kim |
Hurdles for a DRAM-based Match-Action Table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIN ![In: 23rd Conference on Innovation in Clouds, Internet and Networks and Workshops, ICIN 2020, Paris, France, February 24-27, 2020, pp. 13-16, 2020, IEEE, 978-1-7281-5127-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Yifan Qiao |
Design of Database Systems with DRAM-only Heterogeneous Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: 36th IEEE International Conference on Data Engineering, ICDE 2020, Dallas, TX, USA, April 20-24, 2020, pp. 2054-2058, 2020, IEEE, 978-1-7281-2903-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Narek Mamikonyan |
DRAM Structure with Prioritized Memory Bank using Multi-VT Bit Cells Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: IEEE East-West Design & Test Symposium, EWDTS 2020, Varna, Bulgaria, September 4-7, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9899-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Narek Mamikonyan, Nazeli Melikyan, Ruben Musayelyan |
IR Drop Estimation and Optimization on DRAM Memory using Machine Learning Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: IEEE East-West Design & Test Symposium, EWDTS 2020, Varna, Bulgaria, September 4-7, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9899-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Katsushi Kobayashi |
A DRAM-friendly priority queue Internet packet scheduler implementation and its effects on TCP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networking ![In: 2020 IFIP Networking Conference, Networking 2020, Paris, France, June 22-26, 2020, pp. 713-718, 2020, IEEE, 978-3-903176-28-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
13 | Hongtao Zhong, Mingyang Gu, Juejian Wu, Huazhong Yang, Xueqing Li |
Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, pp. 1223-1228, 2020, IEEE, 978-3-9819263-4-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Johannes Feldmann, Kira Kraft, Lukas Steiner, Norbert Wehn, Matthias Jung 0001 |
Fast and Accurate DRAM Simulation: Can we Further Accelerate it? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, pp. 364-369, 2020, IEEE, 978-3-9819263-4-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis |
DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, pp. 298-312, 2020, IEEE, 978-1-7281-7383-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Mingxuan He, Choungki Song, Ilkon Kim, Chunseok Jeong, Seho Kim, Il Park 0001, Mithuna Thottethodi, T. N. Vijaykumar |
Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, pp. 372-385, 2020, IEEE, 978-1-7281-7383-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Jungi Jeong, Jaewan Hong, Seungryoul Maeng, Changhee Jung, Youngjin Kwon |
Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, pp. 525-538, 2020, IEEE, 978-1-7281-7383-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Yaohua Wang, Lois Orosa 0001, Xiangjun Peng, Yang Guo 0003, Saugata Ghose, Minesh Patel, Jeremie S. Kim, Juan Gómez-Luna, Mohammad Sadrosadati, Nika Mansouri-Ghiasi, Onur Mutlu |
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, pp. 313-328, 2020, IEEE, 978-1-7281-7383-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Jie Zhang 0048, Gyuyoung Park, David Donofrio, John Shalf, Myoungsoo Jung |
DRAM-Less: Hardware Acceleration of Data Processing with New Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020, pp. 287-302, 2020, IEEE, 978-1-7281-6149-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Seikwon Kim, Wonsang Kwak, Changdae Kim, Daehyeon Baek, Jaehyuk Huh 0001 |
Charge-Aware DRAM Refresh Reduction with Value Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020, pp. 663-676, 2020, IEEE, 978-1-7281-6149-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Xin Xin 0008, Youtao Zhang, Jun Yang 0002 |
ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020, pp. 303-314, 2020, IEEE, 978-1-7281-6149-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Huiyu Wang, Zhaoyan Shen, Mengying Zhao, Xiaojun Cai, Zhiping Jia |
CLOCK-RWRF: A Read-Write-Relative-Frequency Page Replacement Algorithm for PCM and DRAM of Hybrid Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC/DSS/SmartCity ![In: 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2020, Yanuca Island, Cuvu, Fiji, December 14-16, 2020, pp. 189-196, 2020, IEEE, 978-1-7281-7649-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Michael Garrett Bechtel, Heechul Yun |
Exploiting DRAM bank mapping and HugePages for effective denial-of-service attacks on shared cache in multicore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HotSoS ![In: Proceedings of the 7th Annual Symposium on Hot Topics in the Science of Security, HotSoS 2020, Lawrence, Kansas, USA, September 22-24, 2020, pp. 24:1-24:2, 2020, ACM, 978-1-4503-7561-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Yun-Wei Lin, Chia-Ming Lin |
Optimization of the Deposition Condition for Improving the Ti Film Resistance of DRAM Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SGIoT ![In: Smart Grid and Internet of Things - 4th EAI International Conference, SGIoT 2020, TaiChung, Taiwan, December 5-6, 2020, Proceedings, pp. 527-542, 2020, Springer, 978-3-030-69513-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Seyed Armin Vakil-Ghahani, Mahmut Taylan Kandemir, Jagadish B. Kotra |
DSM: A Case for Hardware-Assisted Merging of DRAM Rows with Same Content. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS (Abstracts) ![In: Abstracts of the 2020 SIGMETRICS/Performance Joint International Conference on Measurement and Modeling of Computer Systems, Boston, MA, USA, June, 8-12, 2020, pp. 91-92, 2020, ACM, 978-1-4503-7985-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Kouki Ozawa, Takahiro Hirofuchi, Ryousei Takano, Midori Sugaya |
fogcached: DRAM-NVM Hybrid Memory-Based KVS Server for Edge Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDGE ![In: Edge Computing - EDGE 2020 - 4th International Conference, Held as Part of the Services Conference Federation, SCF 2020, Honolulu, HI, USA, September 18-20, 2020, Proceedings, pp. 50-62, 2020, Springer, 978-3-030-59823-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Matteo Andreozzi, Frances Conboy, Giovanni Stea, Raffaele Zippo |
Heterogeneous Systems Modelling with Adaptive Traffic Profiles and Its Application to Worst-Case Analysis of a DRAM Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 44th IEEE Annual Computers, Software, and Applications Conference, COMPSAC 2020, Madrid, Spain, July 13-17, 2020, pp. 79-86, 2020, IEEE, 978-1-7281-7303-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Kjersten Criss, Kuljit Bains, Rajat Agarwal, Tanj Bennett, Terry Grunzke, Jangryul Keith Kim, Hoeju Chung, Munseon Jang |
Improving Memory Reliability by Bounding DRAM Faults: DDR5 improved reliability features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: MEMSYS 2020: The International Symposium on Memory Systems, Washington, DC, USA, September, 2020, pp. 317-322, 2020, ACM, 978-1-4503-8899-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad Mohsin Ghaffar, Chirag Sudarshan, Christian Weis, Matthias Jung 0001, Norbert Wehn |
A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: MEMSYS 2020: The International Symposium on Memory Systems, Washington, DC, USA, September, 2020, pp. 158-168, 2020, ACM, 978-1-4503-8899-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Duy Thanh Nguyen, Changhong Min, Nhut-Minh Ho, Ik-Joon Chang |
DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, pp. 47:1-47:8, 2020, IEEE. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Sungsik Park, Yunhong Kim, Woojun Choi, Yong-Tae Lee, Sungbeen Kim, Youngmin Shin, Youngcheol Chae |
A DTMOST-based Temperature Sensor with 3σ Inaccuracy of ±0.9°C for Self-Refresh Control in 28nm Mobile DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2020 IEEE Custom Integrated Circuits Conference, CICC 2020, Boston, MA, USA, March 22-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6031-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Zhiyuan Lv, Youjian Zhao, Chao Zhang 0008, Haibin Li |
DRAMD: Detect Advanced DRAM-based Stealthy Communication Channels with Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: 39th IEEE Conference on Computer Communications, INFOCOM 2020, Toronto, ON, Canada, July 6-9, 2020, pp. 1907-1916, 2020, IEEE, 978-1-7281-6412-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Haerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo |
A Novel In-DRAM Accelerator Architecture for Binary Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COOL CHIPS ![In: 2020 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2020, Kokubunji, Japan, April 15-17, 2020, pp. 1-3, 2020, IEEE, 978-1-7281-6347-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Christos Kalogirou, Christos D. Antonopoulos, Nikolaos Bellas, Spyros Lalis, Lev Mukhanov, Georgios Karakonstantis |
Increasing the Profit of Cloud Providers through DRAM Operation at Reduced Margins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing, CCGRID 2020, Melbourne, Australia, May 11-14, 2020, pp. 549-558, 2020, IEEE, 978-1-7281-6095-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim, So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sang-uhn Cha, Dong-Hak Shin, Jungyu Lee 0002, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yong-Sik Park, Kijun Lee, Myung-Kyu Lee, Seungduk Baek, Junyong Noh, Jae-Wook Lee, Seungseob Lee, Sooyoung Kim, Bo-Tak Lim, Seouk-Kyu Choi, Jin-Guk Kim, Hye-In Choi, Hyuk-Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang-Il Park, Jung-Bae Lee |
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 330-332, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Jaekyu Lee, Seung Sik Kim, In-Gyu Baek, Heesung Shim, Taehoon Kim, Taehyoung Kim, Jungchan Kyoung, Dongmo Im, Jinyong Choi, KeunYeong Cho, Daehoon Kim, Haemin Lim, Min-Woong Seo, JuYoung Kim, Doowon Kwon, Jiyoun Song, Jiyoon Kim, Minho Jang, Joosung Moon, Hyunchul Kim, Chong Kwang Chang, JinGyun Kim, Kyoungmin Koh, Hanjin Lim, JungChak Ahn, Hyeongsun Hong, Kyupil Lee, Ho-Kyu Kang |
5.5 A 2.1e- Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 102-104, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Dong-Uk Lee, Ho Sung Cho, Jihwan Kim, Young Jun Ku, Sangmuk Oh, Chul Dae Kim, Hyun Woo Kim, Wooyoung Lee, Tae-Kyun Kim, Tae Sik Yun, Min Jeong Kim, SeungGyeon Lim, Seong Hee Lee, Byung Kuk Yun, Jun Il Moon, Ji Hwan Park, Seokwoo Choi, Young Jun Park, Chang Kwon Lee, Chunseok Jeong, Jae-Seung Lee, Sang Hun Lee, Woo Sung We, Jong Chan Yun, Doobock Lee, Junghyun Shin, Seungchan Kim, Junghwan Lee, Jiho Choi, Yucheon Ju, Myeong-Jae Park, Kang Seol Lee, Youngdo Hur, Daeyong Shim, Sangkwon Lee, Junhyun Chun, Kyowon Jin |
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 334-336, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim 0003, Dukha Park, Kihan Kim, Sang-Yun Kim 0001, Jinsol Park, Hyunyoon Cho, Sukhyun Lim, YeonKyu Choi, Youngil Lim, Daesik Moon, Geuntae Park, Jin-Hun Jang, Kyungho Lee, Isak Hwang, Cheol Kim, Younghoon Son, Gil-Young Kang, Kiwon Park, Seungjun Lee, Su-Yeon Doo, Chang-Ho Shin, Byongwook Na, Ji-Suk Kwon, Kyung Ryun Kim, Hye-In Choi, Seouk-Kyu Choi, Soobong Chang, Wonil Bae, Hyuck-Joon Kwon, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee |
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 382-384, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Soyeong Shin, Han-Gon Ko, Sungchun Jang, Dongkyun Kim, Deog-Kyoon Jeong |
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 340-342, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Chao-Hsuan Huang, Ishan G. Thakkar |
Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 38th IEEE International Conference on Computer Design, ICCD 2020, Hartford, CT, USA, October 18-21, 2020, pp. 417-420, 2020, IEEE, 978-1-7281-9710-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Yunfang Zhang, Yong Dong, Juan Chen 0001, Zhixin Ou, Yuan Yuan 0034 |
PMC-Based Dynamic Adaptive CPU and DRAM Power Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (1) ![In: Algorithms and Architectures for Parallel Processing - 20th International Conference, ICA3PP 2020, New York City, NY, USA, October 2-4, 2020, Proceedings, Part I, pp. 92-111, 2020, Springer, 978-3-030-60244-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Bashir M. Sabquat Bahar Talukder, Vineetha Menon, Biswajit Ray, Tempestt J. Neal, Md. Tauhidur Rahman 0001 |
Towards the Avoidance of Counterfeit Memory: Identifying the DRAM Origin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2020, San Jose, CA, USA, December 7-11, 2020, pp. 111-121, 2020, IEEE, 978-1-7281-7405-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Brett Meadows, Nathan Edwards, Sang-Yoon Chang |
On-Chip Randomization for Memory Protection Against Hardware Supply Chain Attacks to DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SP (Workshops) ![In: 2020 IEEE Security and Privacy Workshops, SP Workshops, San Francisco, CA, USA, May 21, 2020, pp. 171-180, 2020, IEEE, 978-1-7281-9346-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Christian Helm, Kenjiro Taura |
Automatic Identification and Precise Attribution of DRAM Bandwidth Contention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: ICPP 2020: 49th International Conference on Parallel Processing, Edmonton, AB, Canada, August 17-20, 2020, pp. 34:1-34:11, 2020, ACM, 978-1-4503-8816-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Yifan Qiao, Xubin Chen, Jingpeng Hao, Tong Zhang 0002, Changsheng Xie, Fei Wu 0005 |
Architecting Heterogeneous Memory Systems with DRAM Technology Only: A Case Study on Relational Database. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCHPC@SC ![In: IEEE/ACM Workshop on Memory Centric High Performance Computing, MCHPC@SC 2020, Atlanta, GA, USA, November 11, 2020, pp. 25-33, 2020, IEEE, 978-1-6654-2278-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Steffen Christgau, Thomas Steinke 0001 |
Leveraging a Heterogeneous Memory System for a Legacy Fortran Code: The Interplay of Storage Class Memory, DRAM and OS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCHPC@SC ![In: IEEE/ACM Workshop on Memory Centric High Performance Computing, MCHPC@SC 2020, Atlanta, GA, USA, November 11, 2020, pp. 17-24, 2020, IEEE, 978-1-6654-2278-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Isaac Boixaderas, Darko Zivanovic, Sergi Moré, Javier Bartolome, David Vicente, Marc Casas, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé |
Cost-aware prediction of uncorrected DRAM errors in the field. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2020, Virtual Event / Atlanta, Georgia, USA, November 9-19, 2020, pp. 61, 2020, IEEE/ACM, 978-1-7281-9998-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Lucas Matana Luza, Daniel Söderström, Helmut Puchner, Rubén García Alía, Manon Letiche, Alberto Bosio, Luigi Dilillo |
Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 15th Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2020, Marrakech, Morocco, April 1-3, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-5426-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Jeremie S. Kim, Minesh Patel, Abdullah Giray Yaglikçi, Hasan Hassan, Roknoddin Azizi, Lois Orosa 0001, Onur Mutlu |
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020, Virtual Event / Valencia, Spain, May 30 - June 3, 2020, pp. 638-651, 2020, IEEE, 978-1-7281-4661-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Sangmok Jeong, SeungYup Kang, Joon-Sung Yang |
PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Payman Behnam, Mahdi Nazm Bojnordi |
RedCache: Reduced DRAM Caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001 |
DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Minghua Wang, Zhi Zhang 0001, Yueqiang Cheng, Surya Nepal |
DRAMDig: A Knowledge-assisted Tool to Uncover DRAM Address Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Xin Xin 0008, Youtao Zhang, Jun Yang 0002 |
Reducing DRAM Access Latency via Helper Rows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Saugata Ghose, Tianshi Li 0001, Nastaran Hajinazar, Damla Senol Cali, Onur Mutlu |
Demystifying Complex Workload-DRAM Interactions: An Experimental Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Meas. Anal. Comput. Syst. ![In: Proc. ACM Meas. Anal. Comput. Syst. 3(3), pp. 60:1-60:50, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, ChanYong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin |
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(1), pp. 197-209, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Seunghak Lee, Nam Sung Kim, Daehoon Kim |
Exploiting OS-Level Memory Offlining for DRAM Power Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 18(2), pp. 141-144, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Yicheng Wang, Yang Liu 0114, Peiyun Wu, Zhao Zhang 0008 |
Detect DRAM Disturbance Error by Using Disturbance Bin Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 18(1), pp. 34-37, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Konstantinos Tovletoglou, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis |
Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 18(1), pp. 26-29, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Kate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, Xun Jian 0002 |
Nonblocking DRAM Refresh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 39(3), pp. 103-109, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Bill Gervasi |
Will Carbon Nanotube Memory Replace DRAM? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 39(2), pp. 45-51, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Bashir M. Sabquat Bahar Talukder, Biswajit Ray, Domenic Forte, Md. Tauhidur Rahman 0001 |
PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 81106-81120, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Carlos Navarro, Carlos Marquez, Santiago Navarro, Carmen Lozano, Sehyun Kwon, Yong-Tae Kim, Francisco Gámiz |
Simulation Perspectives of Sub-1V Single-Supply Z2-FET 1T-DRAM Cells for Low-Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 40279-40284, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Jongsun Park 0001, Il Park 0001, Seon Wook Kim |
Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 82633-82648, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Na Niu, Fangfa Fu, Bing Yang, Jiacai Yuan, Fengchang Lai, Jinxiang Wang 0001 |
WIRD: An Efficiency Migration Scheme in Hybrid DRAM and PCM Main Memory for Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 35941-35951, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki |
Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 75500-75514, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Akhil James, Sneh Saurabh |
Dopingless 1T DRAM: Proposal, Design, and Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 88960-88969, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Andrew J. Douglass, Sunil P. Khatri |
Fast, Ring-Based Design of 3-D Stacked DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(8), pp. 1731-1741, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Suk Min Kim, Byungkyu Song, Seong-Ook Jung |
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(10), pp. 2413-2422, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Fazal Hameed, Jerónimo Castrillón |
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(10), pp. 2375-2386, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim |
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(4), pp. 978-982, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Yongwoon Song, Dongkeon Choi, Hyuk-Jun Lee |
Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 102-C(12), pp. 849-852, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Reza Salkhordeh, Onur Mutlu, Hossein Asadi 0001 |
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(8), pp. 1114-1130, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Yuhai Cao, Chao Li 0009, Jing Wang 0055, Weigong Zhang, Quan Chen 0002, Jingwen Leng, Bin Yao 0002, Yao Shen, Minyi Guo |
DR Refresh: Releasing DRAM Potential by Enabling Read Accesses Under Refresh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(11), pp. 1584-1596, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Moonsoo Kim, Jungwoo Choi, Hyun Kim 0001, Hyuk-Jae Lee |
An Effective DRAM Address Remapping for Mitigating Rowhammer Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(10), pp. 1428-1441, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shibo Wang, Mahdi Nazm Bojnordi, Xiaochen Guo, Engin Ipek |
Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(3), pp. 362-374, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Sheng Ma, Zhong Liu, Shenggang Chen, Libo Huang, Yang Guo 0003, Zhiying Wang 0003, Meidi Zhang |
Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 30(10), pp. 2148-2164, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Ming Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi |
Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 64, pp. 159-169, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Rajasekhar Turaka, M. Satya Sai Ram |
Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 69, pp. 92-100, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Sanghoon Cha, Bokyeong Kim, Chang Hyun Park 0001, Jaehyuk Huh 0001 |
Morphable DRAM Cache Design for Hybrid Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 16(3), pp. 31:1-31:24, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis |
Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 15(4), pp. 65:1-65:23, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase |
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 35(4), pp. 485-495, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Su-Kyung Yoon, Young-Sun Youn, Bernd Burgstaller, Shin-Dug Kim |
Self-learnable Cluster-based Prefetching Method for DRAM-Flash Hybrid Main Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 15(1), pp. 10:1-10:21, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Sherif M. Sharroush |
A predischarged bitline 1T-1C DRAM readout scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 83, pp. 168-184, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Kyu Hyun Choi, Jaeyung Jun, Minseong Kim, Seon Wook Kim |
Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(5), pp. 53:1-53:31, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh 0002, Partha S. Roop |
Formal Modeling and Verification of a Victim DRAM Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(2), pp. 20:1-20:23, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Yang Song 0006, Olivier Alavoine, Bill Lin 0001 |
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(1), pp. 5:1-5:27, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | David Wood, James H. Cole, Thomas C. Booth |
NEURO-DRAM: a 3D recurrent visual attention model for interpretable neuroimaging classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1910.04721, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Vinson Young, Zeshan Chishti, Moinuddin K. Qureshi |
TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1907.02184, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Saugata Ghose, Tianshi Li 0001, Nastaran Hajinazar, Damla Senol Cali, Onur Mutlu |
Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.07609, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Dimitrios Stathis 0001, Chirag Sudarshan, Yu Yang, Matthias Jung 0001, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn |
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1911.00889, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Vinson Young, Moinuddin K. Qureshi |
To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1907.02167, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Ravikiran Yeleswarapu, Arun K. Somani |
Addressing multiple bit/symbol errors in DRAM subsystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1908.01806, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Reza Salkhordeh, Onur Mutlu, Hossein Asadi 0001 |
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1903.10067, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Nima Karimian, Fatemeh Tehranipoor, Nikolaos A. Anagnostopoulos, Wei Yan 0005 |
DRAMNet: Authentication based on Physical Unique Features of DRAM Using Deep Convolutional Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.09094, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Bashir M. Sabquat Bahar Talukder, Vineetha Menon, Biswajit Ray, Tempestt J. Neal, Md. Tauhidur Rahman 0001 |
Towards the Avoidance of Counterfeit Memory: Identifying the DRAM Origin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1911.03395, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Md. Hasan Raza Ansari, Jawar Singh |
Improvement in Retention Time of Capacitorless DRAM with Access Transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1910.03907, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Se Kwon Lee, Jayashree Mohan, Sanidhya Kashyap, Taesoo Kim, Vijay Chidambaram |
RECIPE : Converting Concurrent DRAM Indexes to Persistent-Memory Indexes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1909.13670, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Lois Orosa 0001, Yaohua Wang, Ivan Puddu, Mohammad Sadrosadati, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Arash Tavakkol, Minesh Patel, Jeremie S. Kim, Vivek Seshadri, Uksong Kang, Saugata Ghose, Rodolfo Azevedo, Onur Mutlu |
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.07344, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Shaahin Angizi, Deliang Fan |
Accelerating Bulk Bit-Wise X(N)OR Operation in Processing-in-DRAM Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1904.05782, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Anirban Chakraborty 0003, Sarani Bhattacharya, Debdeep Mukhopadhyay |
Using Memory Allocation Schemes in Linux to Exploit DRAM Vulnerability: with Rowhammer as a Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1905.12974, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | RhongHo Jang, Seongkwang Moon, Youngtae Noh, Aziz Mohaisen, DaeHun Nyang |
Scaling Up Anomaly Detection Using In-DRAM Working Set of Active Flows Table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.04143, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Skanda Koppula, Lois Orosa 0001, Abdullah Giray Yaglikçi, Roknoddin Azizi, Taha Shahroodi, Konstantinos Kanellopoulos, Onur Mutlu |
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1910.05340, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Vivek Seshadri, Onur Mutlu |
In-DRAM Bulk Bitwise Execution Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1905.09822, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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13 | Wenjie Huang, Weiguo Tang, Junlin Chen, Lei Wang 0003 |
Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 66-II(8), pp. 1391-1395, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
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