Search results for "DRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Christian Helm, Soramichi Akiyama, Kenjiro Taura	Reliable Reverse Engineering of Intel DRAM Addressing Using Performance Counters.	MASCOTS	2020	DBLP DOI BibTeX RDF
13	Onkar Patil, Frank Mueller 0001, Latchesar Ionkov, Jason Lee, Michael Lang 0003	Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory.	MASCOTS	2020	DBLP DOI BibTeX RDF
13	Curt Beckmann, Ramkumar Krishnamoorthy, Han Wang 0009, Andre Lam, Changhoon Kim	Hurdles for a DRAM-based Match-Action Table.	ICIN	2020	DBLP DOI BibTeX RDF
13	Yifan Qiao	Design of Database Systems with DRAM-only Heterogeneous Memory Architecture.	ICDE	2020	DBLP DOI BibTeX RDF
13	Narek Mamikonyan	DRAM Structure with Prioritized Memory Bank using Multi-VT Bit Cells Architecture.	EWDTS	2020	DBLP DOI BibTeX RDF
13	Narek Mamikonyan, Nazeli Melikyan, Ruben Musayelyan	IR Drop Estimation and Optimization on DRAM Memory using Machine Learning Algorithms.	EWDTS	2020	DBLP DOI BibTeX RDF
13	Katsushi Kobayashi	A DRAM-friendly priority queue Internet packet scheduler implementation and its effects on TCP.	Networking	2020	DBLP BibTeX RDF
13	Hongtao Zhong, Mingyang Gu, Juejian Wu, Huazhong Yang, Xueqing Li	Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices.	DATE	2020	DBLP DOI BibTeX RDF
13	Johannes Feldmann, Kira Kraft, Lukas Steiner, Norbert Wehn, Matthias Jung 0001	Fast and Accurate DRAM Simulation: Can we Further Accelerate it?	DATE	2020	DBLP DOI BibTeX RDF
13	Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis	DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms.	MICRO	2020	DBLP DOI BibTeX RDF
13	Mingxuan He, Choungki Song, Ilkon Kim, Chunseok Jeong, Seho Kim, Il Park 0001, Mithuna Thottethodi, T. N. Vijaykumar	Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning.	MICRO	2020	DBLP DOI BibTeX RDF
13	Jungi Jeong, Jaewan Hong, Seungryoul Maeng, Changhee Jung, Youngjin Kwon	Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System.	MICRO	2020	DBLP DOI BibTeX RDF
13	Yaohua Wang, Lois Orosa 0001, Xiangjun Peng, Yang Guo 0003, Saugata Ghose, Minesh Patel, Jeremie S. Kim, Juan Gómez-Luna, Mohammad Sadrosadati, Nika Mansouri-Ghiasi, Onur Mutlu	FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.	MICRO	2020	DBLP DOI BibTeX RDF
13	Jie Zhang 0048, Gyuyoung Park, David Donofrio, John Shalf, Myoungsoo Jung	DRAM-Less: Hardware Acceleration of Data Processing with New Memory.	HPCA	2020	DBLP DOI BibTeX RDF
13	Seikwon Kim, Wonsang Kwak, Changdae Kim, Daehyeon Baek, Jaehyuk Huh 0001	Charge-Aware DRAM Refresh Reduction with Value Transformation.	HPCA	2020	DBLP DOI BibTeX RDF
13	Xin Xin 0008, Youtao Zhang, Jun Yang 0002	ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM.	HPCA	2020	DBLP DOI BibTeX RDF
13	Huiyu Wang, Zhaoyan Shen, Mengying Zhao, Xiaojun Cai, Zhiping Jia	CLOCK-RWRF: A Read-Write-Relative-Frequency Page Replacement Algorithm for PCM and DRAM of Hybrid Memory.	HPCC/DSS/SmartCity	2020	DBLP DOI BibTeX RDF
13	Michael Garrett Bechtel, Heechul Yun	Exploiting DRAM bank mapping and HugePages for effective denial-of-service attacks on shared cache in multicore.	HotSoS	2020	DBLP DOI BibTeX RDF
13	Yun-Wei Lin, Chia-Ming Lin	Optimization of the Deposition Condition for Improving the Ti Film Resistance of DRAM Products.	SGIoT	2020	DBLP DOI BibTeX RDF
13	Seyed Armin Vakil-Ghahani, Mahmut Taylan Kandemir, Jagadish B. Kotra	DSM: A Case for Hardware-Assisted Merging of DRAM Rows with Same Content.	SIGMETRICS (Abstracts)	2020	DBLP DOI BibTeX RDF
13	Kouki Ozawa, Takahiro Hirofuchi, Ryousei Takano, Midori Sugaya	fogcached: DRAM-NVM Hybrid Memory-Based KVS Server for Edge Computing.	EDGE	2020	DBLP DOI BibTeX RDF
13	Matteo Andreozzi, Frances Conboy, Giovanni Stea, Raffaele Zippo	Heterogeneous Systems Modelling with Adaptive Traffic Profiles and Its Application to Worst-Case Analysis of a DRAM Controller.	COMPSAC	2020	DBLP DOI BibTeX RDF
13	Kjersten Criss, Kuljit Bains, Rajat Agarwal, Tanj Bennett, Terry Grunzke, Jangryul Keith Kim, Hoeju Chung, Munseon Jang	Improving Memory Reliability by Bounding DRAM Faults: DDR5 improved reliability features.	MEMSYS	2020	DBLP DOI BibTeX RDF
13	Muhammad Mohsin Ghaffar, Chirag Sudarshan, Christian Weis, Matthias Jung 0001, Norbert Wehn	A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions.	MEMSYS	2020	DBLP DOI BibTeX RDF
13	Duy Thanh Nguyen, Changhong Min, Nhut-Minh Ho, Ik-Joon Chang	DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System.	ICCAD	2020	DBLP DOI BibTeX RDF
13	Sungsik Park, Yunhong Kim, Woojun Choi, Yong-Tae Lee, Sungbeen Kim, Youngmin Shin, Youngcheol Chae	A DTMOST-based Temperature Sensor with 3σ Inaccuracy of ±0.9°C for Self-Refresh Control in 28nm Mobile DRAM.	CICC	2020	DBLP DOI BibTeX RDF
13	Zhiyuan Lv, Youjian Zhao, Chao Zhang 0008, Haibin Li	DRAMD: Detect Advanced DRAM-based Stealthy Communication Channels with Neural Networks.	INFOCOM	2020	DBLP DOI BibTeX RDF
13	Haerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo	A Novel In-DRAM Accelerator Architecture for Binary Neural Network.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
13	Christos Kalogirou, Christos D. Antonopoulos, Nikolaos Bellas, Spyros Lalis, Lev Mukhanov, Georgios Karakonstantis	Increasing the Profit of Cloud Providers through DRAM Operation at Reduced Margins.	CCGRID	2020	DBLP DOI BibTeX RDF
13	Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim, So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sang-uhn Cha, Dong-Hak Shin, Jungyu Lee 0002, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yong-Sik Park, Kijun Lee, Myung-Kyu Lee, Seungduk Baek, Junyong Noh, Jae-Wook Lee, Seungseob Lee, Sooyoung Kim, Bo-Tak Lim, Seouk-Kyu Choi, Jin-Guk Kim, Hye-In Choi, Hyuk-Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang-Il Park, Jung-Bae Lee	22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.	ISSCC	2020	DBLP DOI BibTeX RDF
13	Jaekyu Lee, Seung Sik Kim, In-Gyu Baek, Heesung Shim, Taehoon Kim, Taehyoung Kim, Jungchan Kyoung, Dongmo Im, Jinyong Choi, KeunYeong Cho, Daehoon Kim, Haemin Lim, Min-Woong Seo, JuYoung Kim, Doowon Kwon, Jiyoun Song, Jiyoon Kim, Minho Jang, Joosung Moon, Hyunchul Kim, Chong Kwang Chang, JinGyun Kim, Kyoungmin Koh, Hanjin Lim, JungChak Ahn, Hyeongsun Hong, Kyupil Lee, Ho-Kyu Kang	5.5 A 2.1e- Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology.	ISSCC	2020	DBLP DOI BibTeX RDF
13	Dong-Uk Lee, Ho Sung Cho, Jihwan Kim, Young Jun Ku, Sangmuk Oh, Chul Dae Kim, Hyun Woo Kim, Wooyoung Lee, Tae-Kyun Kim, Tae Sik Yun, Min Jeong Kim, SeungGyeon Lim, Seong Hee Lee, Byung Kuk Yun, Jun Il Moon, Ji Hwan Park, Seokwoo Choi, Young Jun Park, Chang Kwon Lee, Chunseok Jeong, Jae-Seung Lee, Sang Hun Lee, Woo Sung We, Jong Chan Yun, Doobock Lee, Junghyun Shin, Seungchan Kim, Junghwan Lee, Jiho Choi, Yucheon Ju, Myeong-Jae Park, Kang Seol Lee, Youngdo Hur, Daeyong Shim, Sangkwon Lee, Junhyun Chun, Kyowon Jin	22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.	ISSCC	2020	DBLP DOI BibTeX RDF
13	Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim 0003, Dukha Park, Kihan Kim, Sang-Yun Kim 0001, Jinsol Park, Hyunyoon Cho, Sukhyun Lim, YeonKyu Choi, Youngil Lim, Daesik Moon, Geuntae Park, Jin-Hun Jang, Kyungho Lee, Isak Hwang, Cheol Kim, Younghoon Son, Gil-Young Kang, Kiwon Park, Seungjun Lee, Su-Yeon Doo, Chang-Ho Shin, Byongwook Na, Ji-Suk Kwon, Kyung Ryun Kim, Hye-In Choi, Seouk-Kyu Choi, Soobong Chang, Wonil Bae, Hyuck-Joon Kwon, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee	22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.	ISSCC	2020	DBLP DOI BibTeX RDF
13	Soyeong Shin, Han-Gon Ko, Sungchun Jang, Dongkyun Kim, Deog-Kyoon Jeong	22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface.	ISSCC	2020	DBLP DOI BibTeX RDF
13	Chao-Hsuan Huang, Ishan G. Thakkar	Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration.	ICCD	2020	DBLP DOI BibTeX RDF
13	Yunfang Zhang, Yong Dong, Juan Chen 0001, Zhixin Ou, Yuan Yuan 0034	PMC-Based Dynamic Adaptive CPU and DRAM Power Modeling.	ICA3PP (1)	2020	DBLP DOI BibTeX RDF
13	Bashir M. Sabquat Bahar Talukder, Vineetha Menon, Biswajit Ray, Tempestt J. Neal, Md. Tauhidur Rahman 0001	Towards the Avoidance of Counterfeit Memory: Identifying the DRAM Origin.	HOST	2020	DBLP DOI BibTeX RDF
13	Brett Meadows, Nathan Edwards, Sang-Yoon Chang	On-Chip Randomization for Memory Protection Against Hardware Supply Chain Attacks to DRAM.	SP (Workshops)	2020	DBLP DOI BibTeX RDF
13	Christian Helm, Kenjiro Taura	Automatic Identification and Precise Attribution of DRAM Bandwidth Contention.	ICPP	2020	DBLP DOI BibTeX RDF
13	Yifan Qiao, Xubin Chen, Jingpeng Hao, Tong Zhang 0002, Changsheng Xie, Fei Wu 0005	Architecting Heterogeneous Memory Systems with DRAM Technology Only: A Case Study on Relational Database.	MCHPC@SC	2020	DBLP DOI BibTeX RDF
13	Steffen Christgau, Thomas Steinke 0001	Leveraging a Heterogeneous Memory System for a Legacy Fortran Code: The Interplay of Storage Class Memory, DRAM and OS.	MCHPC@SC	2020	DBLP DOI BibTeX RDF
13	Isaac Boixaderas, Darko Zivanovic, Sergi Moré, Javier Bartolome, David Vicente, Marc Casas, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé	Cost-aware prediction of uncorrected DRAM errors in the field.	SC	2020	DBLP DOI BibTeX RDF
13	Lucas Matana Luza, Daniel Söderström, Helmut Puchner, Rubén García Alía, Manon Letiche, Alberto Bosio, Luigi Dilillo	Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM.	DTIS	2020	DBLP DOI BibTeX RDF
13	Jeremie S. Kim, Minesh Patel, Abdullah Giray Yaglikçi, Hasan Hassan, Roknoddin Azizi, Lois Orosa 0001, Onur Mutlu	Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques.	ISCA	2020	DBLP DOI BibTeX RDF
13	Sangmok Jeong, SeungYup Kang, Joon-Sung Yang	PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code.	DAC	2020	DBLP DOI BibTeX RDF
13	Payman Behnam, Mahdi Nazm Bojnordi	RedCache: Reduced DRAM Caching.	DAC	2020	DBLP DOI BibTeX RDF
13	Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001	DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks.	DAC	2020	DBLP DOI BibTeX RDF
13	Minghua Wang, Zhi Zhang 0001, Yueqiang Cheng, Surya Nepal	DRAMDig: A Knowledge-assisted Tool to Uncover DRAM Address Mapping.	DAC	2020	DBLP DOI BibTeX RDF
13	Xin Xin 0008, Youtao Zhang, Jun Yang 0002	Reducing DRAM Access Latency via Helper Rows.	DAC	2020	DBLP DOI BibTeX RDF
13	Saugata Ghose, Tianshi Li 0001, Nastaran Hajinazar, Damla Senol Cali, Onur Mutlu	Demystifying Complex Workload-DRAM Interactions: An Experimental Study.	Proc. ACM Meas. Anal. Comput. Syst.	2019	DBLP DOI BibTeX RDF
13	Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, ChanYong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin	A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
13	Seunghak Lee, Nam Sung Kim, Daehoon Kim	Exploiting OS-Level Memory Offlining for DRAM Power Management.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
13	Yicheng Wang, Yang Liu 0114, Peiyun Wu, Zhao Zhang 0008	Detect DRAM Disturbance Error by Using Disturbance Bin Counters.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
13	Konstantinos Tovletoglou, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis	Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
13	Kate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, Xun Jian 0002	Nonblocking DRAM Refresh.	IEEE Micro	2019	DBLP DOI BibTeX RDF
13	Bill Gervasi	Will Carbon Nanotube Memory Replace DRAM?	IEEE Micro	2019	DBLP DOI BibTeX RDF
13	Bashir M. Sabquat Bahar Talukder, Biswajit Ray, Domenic Forte, Md. Tauhidur Rahman 0001	PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures.	IEEE Access	2019	DBLP DOI BibTeX RDF
13	Carlos Navarro, Carlos Marquez, Santiago Navarro, Carmen Lozano, Sehyun Kwon, Yong-Tae Kim, Francisco Gámiz	Simulation Perspectives of Sub-1V Single-Supply Z2-FET 1T-DRAM Cells for Low-Power.	IEEE Access	2019	DBLP DOI BibTeX RDF
13	Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Jongsun Park 0001, Il Park 0001, Seon Wook Kim	Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors.	IEEE Access	2019	DBLP DOI BibTeX RDF
13	Na Niu, Fangfa Fu, Bing Yang, Jiacai Yuan, Fengchang Lai, Jinxiang Wang 0001	WIRD: An Efficiency Migration Scheme in Hybrid DRAM and PCM Main Memory for Image Processing Applications.	IEEE Access	2019	DBLP DOI BibTeX RDF
13	Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki	Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis.	IEEE Access	2019	DBLP DOI BibTeX RDF
13	Akhil James, Sneh Saurabh	Dopingless 1T DRAM: Proposal, Design, and Analysis.	IEEE Access	2019	DBLP DOI BibTeX RDF
13	Andrew J. Douglass, Sunil P. Khatri	Fast, Ring-Based Design of 3-D Stacked DRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
13	Suk Min Kim, Byungkyu Song, Seong-Ook Jung	Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
13	Fazal Hameed, Jerónimo Castrillón	A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
13	Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim	A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
13	Yongwoon Song, Dongkeon Choi, Hyuk-Jun Lee	Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers.	IEICE Trans. Electron.	2019	DBLP DOI BibTeX RDF
13	Reza Salkhordeh, Onur Mutlu, Hossein Asadi 0001	An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
13	Yuhai Cao, Chao Li 0009, Jing Wang 0055, Weigong Zhang, Quan Chen 0002, Jingwen Leng, Bin Yao 0002, Yao Shen, Minyi Guo	DR Refresh: Releasing DRAM Potential by Enabling Read Accesses Under Refresh.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
13	Moonsoo Kim, Jungwoo Choi, Hyun Kim 0001, Hyuk-Jae Lee	An Effective DRAM Address Remapping for Mitigating Rowhammer Errors.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
13	Shibo Wang, Mahdi Nazm Bojnordi, Xiaochen Guo, Engin Ipek	Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
13	Sheng Ma, Zhong Liu, Shenggang Chen, Libo Huang, Yang Guo 0003, Zhiying Wang 0003, Meidi Zhang	Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication.	IEEE Trans. Parallel Distributed Syst.	2019	DBLP DOI BibTeX RDF
13	Ming Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi	Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
13	Rajasekhar Turaka, M. Satya Sai Ram	Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
13	Sanghoon Cha, Bokyeong Kim, Chang Hyun Park 0001, Jaehyuk Huh 0001	Morphable DRAM Cache Design for Hybrid Memory Systems.	ACM Trans. Archit. Code Optim.	2019	DBLP DOI BibTeX RDF
13	Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis	Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache.	ACM Trans. Archit. Code Optim.	2019	DBLP DOI BibTeX RDF
13	Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase	Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
13	Su-Kyung Yoon, Young-Sun Youn, Bernd Burgstaller, Shin-Dug Kim	Self-learnable Cluster-based Prefetching Method for DRAM-Flash Hybrid Main Memory Architecture.	ACM J. Emerg. Technol. Comput. Syst.	2019	DBLP DOI BibTeX RDF
13	Sherif M. Sharroush	A predischarged bitline 1T-1C DRAM readout scheme.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
13	Kyu Hyun Choi, Jaeyung Jun, Minseong Kim, Seon Wook Kim	Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy Repair.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
13	Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh 0002, Partha S. Roop	Formal Modeling and Verification of a Victim DRAM Cache.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
13	Yang Song 0006, Olivier Alavoine, Bill Lin 0001	Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
13	David Wood, James H. Cole, Thomas C. Booth	NEURO-DRAM: a 3D recurrent visual attention model for interpretable neuroimaging classification.	CoRR	2019	DBLP BibTeX RDF
13	Vinson Young, Zeshan Chishti, Moinuddin K. Qureshi	TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems.	CoRR	2019	DBLP BibTeX RDF
13	Saugata Ghose, Tianshi Li 0001, Nastaran Hajinazar, Damla Senol Cali, Onur Mutlu	Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study.	CoRR	2019	DBLP BibTeX RDF
13	Dimitrios Stathis 0001, Chirag Sudarshan, Yu Yang, Matthias Jung 0001, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn	eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.	CoRR	2019	DBLP BibTeX RDF
13	Vinson Young, Moinuddin K. Qureshi	To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches.	CoRR	2019	DBLP BibTeX RDF
13	Ravikiran Yeleswarapu, Arun K. Somani	Addressing multiple bit/symbol errors in DRAM subsystem.	CoRR	2019	DBLP BibTeX RDF
13	Reza Salkhordeh, Onur Mutlu, Hossein Asadi 0001	An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories.	CoRR	2019	DBLP BibTeX RDF
13	Nima Karimian, Fatemeh Tehranipoor, Nikolaos A. Anagnostopoulos, Wei Yan 0005	DRAMNet: Authentication based on Physical Unique Features of DRAM Using Deep Convolutional Neural Networks.	CoRR	2019	DBLP BibTeX RDF
13	Bashir M. Sabquat Bahar Talukder, Vineetha Menon, Biswajit Ray, Tempestt J. Neal, Md. Tauhidur Rahman 0001	Towards the Avoidance of Counterfeit Memory: Identifying the DRAM Origin.	CoRR	2019	DBLP BibTeX RDF
13	Md. Hasan Raza Ansari, Jawar Singh	Improvement in Retention Time of Capacitorless DRAM with Access Transistor.	CoRR	2019	DBLP BibTeX RDF
13	Se Kwon Lee, Jayashree Mohan, Sanidhya Kashyap, Taesoo Kim, Vijay Chidambaram	RECIPE : Converting Concurrent DRAM Indexes to Persistent-Memory Indexes.	CoRR	2019	DBLP BibTeX RDF
13	Lois Orosa 0001, Yaohua Wang, Ivan Puddu, Mohammad Sadrosadati, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Arash Tavakkol, Minesh Patel, Jeremie S. Kim, Vivek Seshadri, Uksong Kang, Saugata Ghose, Rodolfo Azevedo, Onur Mutlu	Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.	CoRR	2019	DBLP BibTeX RDF
13	Shaahin Angizi, Deliang Fan	Accelerating Bulk Bit-Wise X(N)OR Operation in Processing-in-DRAM Platform.	CoRR	2019	DBLP BibTeX RDF
13	Anirban Chakraborty 0003, Sarani Bhattacharya, Debdeep Mukhopadhyay	Using Memory Allocation Schemes in Linux to Exploit DRAM Vulnerability: with Rowhammer as a Case Study.	CoRR	2019	DBLP BibTeX RDF
13	RhongHo Jang, Seongkwang Moon, Youngtae Noh, Aziz Mohaisen, DaeHun Nyang	Scaling Up Anomaly Detection Using In-DRAM Working Set of Active Flows Table.	CoRR	2019	DBLP BibTeX RDF
13	Skanda Koppula, Lois Orosa 0001, Abdullah Giray Yaglikçi, Roknoddin Azizi, Taha Shahroodi, Konstantinos Kanellopoulos, Onur Mutlu	EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM.	CoRR	2019	DBLP BibTeX RDF
13	Vivek Seshadri, Onur Mutlu	In-DRAM Bulk Bitwise Execution Engine.	CoRR	2019	DBLP BibTeX RDF
13	Wenjie Huang, Weiguo Tang, Junlin Chen, Lei Wang 0003	Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF