Search results for "FCCM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose	FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.	FCCM	2009	DBLP DOI BibTeX RDF	photodynamic therapy, PDT, Stratix, DE3, FPGA, applications, pipeline, Power, Monte Carlo, SystemC, acceleration, cancer
1	Stephen Longfield Jr., Mark L. Chang	A Parameterized Stereo Vision Core for FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	Field programmable gate arrays, Reconfigurable computing, Stereo vision
1	Tobias Schumacher 0001, Christian Plessl, Marco Platzner	IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, Network-on-Chip, Performance Monitoring
1	Anson H. T. Tse, David B. Thomas, Wayne Luk	Accelerating Quadrature Methods for Option Valuation.	FCCM	2009	DBLP DOI BibTeX RDF	Option Valuation, Finance, Option pricing, Quadrature
1	Deepak Unnikrishnan, Jia Zhao, Russell Tessier	Application Specific Customization and Scalability of Soft Multiprocessors.	FCCM	2009	DBLP DOI BibTeX RDF	soft multiprocessor, application specific customization, FPGA, architectural evaluation, automatic compilation
1	Chih-Hung Wu, Seda Ogrenci Memik, Sanjay Mehrotra	FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection.	FCCM	2009	DBLP DOI BibTeX RDF	interior point, inter-frame collision, linear programming
1	Samuel Antao, Ricardo Chaves, Leonel Sousa	Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices.	FCCM	2009	DBLP DOI BibTeX RDF	Cryptography, Elliptic Curve, Reconfigurable Hardware, Microcode
1	Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne	FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation.	FCCM	2009	DBLP DOI BibTeX RDF
1	Dirk Koch, Christian Beckhoff, Jürgen Teich	Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems.	FCCM	2009	DBLP DOI BibTeX RDF
1	Qingbo Wang, Viktor K. Prasanna	Multi-Core Architecture on FPGA for Large Dictionary String Matching.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, String Matching, Multi-core Architecture
1	Jong-Ho Byun, Arun Ravindran, Arindam Mukherjee 0001, Bharat Joshi, David Chassin	Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer.	FCCM	2009	DBLP DOI BibTeX RDF	power flow computing, Gauss-Seidel, bus voltage computations, FPGA, reconfigurable computing
1	Jason Wu, John Williams 0004, Neil W. Bergmann, Peter Sutton	Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, MPSoC, JPEG
1	Amir Hossein Gholamipour, Hamid Eslami, Ahmed M. Eltawil, Fadi J. Kurdahi	Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems.	FCCM	2009	DBLP DOI BibTeX RDF
1	Kyle Rupnow, Wenyin Fu, Katherine Compton	Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-Tasking.	FCCM	2009	DBLP DOI BibTeX RDF
1	Yi-Hua Edward Yang, Viktor K. Prasanna	Memory-Efficient Pipelined Architecture for Large-Scale String Matching.	FCCM	2009	DBLP DOI BibTeX RDF
1	Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier	Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators.	FCCM	2009	DBLP DOI BibTeX RDF
1	Hoang Le, Viktor K. Prasanna	Scalable High Throughput and Power Efficient IP-Lookup on FPGA.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, Network, Energy Efficiency, Router, Power Saving, IP Lookup, Trie, BST
1	Rafael García, Ann Gordon-Ross, Alan D. George	Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks.	FCCM	2009	DBLP DOI BibTeX RDF	virtual architecture, FPGA, reconfigurable computing, Kalman filter, partial reconfiguration
1	Nachiket Kapre, André DeHon	Accelerating SPICE Model-Evaluation using FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	Analog Circuit Simulator, VLIW Scheduling, Floating-Point, Spice, Loop Unrolling, Spatial Computation
1	Kenneth L. Pocek, Duncan A. Buell (eds.)	FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings	FCCM	2009	DBLP BibTeX RDF
1	Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf	A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines.	FCCM	2009	DBLP DOI BibTeX RDF	Machine Learning, FPGAs, Support Vector Machines, Parallel Architectures, Hardware Acceleration
1	Philip Garcia, Katherine Compton	Shared Memory Cache Organizations for Reconfigurable Computing Systems.	FCCM	2009	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, William V. Kritikos, Rahul R. Sharma, Ron Sass	AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, network, high performance computing, reconfigurable computing
1	Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Ghazawi	Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants.	FCCM	2009	DBLP DOI BibTeX RDF	Hardware task mapping, genetic algorithm, reconfigurable computing
1	Margaret A. Sullivan, Herschel H. Loomis Jr., Alan A. Ross	Employment of Reduced Precision Redundancy for Fault Tolerant FPGA Applications.	FCCM	2009	DBLP DOI BibTeX RDF	Fault-tolerant Logic, Reduced Precision Redundancy, FPGA, Space-based Computing
1	Anthony E. Gregerson, Amin Farmahini Farahani, Ben Buchli, Steve Naumov, Michail Bachtis, Katherine Compton, Michael J. Schulte, Wesley H. Smith, Sridhara Dasu	FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron Collider.	FCCM	2009	DBLP DOI BibTeX RDF
1	Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede	Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, monitoring, debug, transaction, instrumentation
1	Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou 0007, Miao Wang, Jingfei Jiang	A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF
1	Jin H. Park, Yunfei Qiu, Martin C. Herbordt	CAAD BLASTP: NCBI BLASTP Accelerated with FPGA-Based Accelerated Pre-Filtering.	FCCM	2009	DBLP DOI BibTeX RDF
1	Holger Lange, Florian Stock, Andreas Koch 0001, Dietmar Hildenbrand	Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, GPU, Inverse Kinematic, Geometric Algebra
1	Joon Edward Sim, Weng-Fai Wong, Jürgen Teich	Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators.	FCCM	2009	DBLP DOI BibTeX RDF	Reconfiguration Scheduling, FPGA, Reconfigurable Computing, Partial Reconfiguration
1	Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen	Benchmarking Reconfigurable Architectures in the Mobile Domain.	FCCM	2009	DBLP DOI BibTeX RDF	Mobile Domain, FPGA, Low Power, Reconfigurable Architectures
1	Martin Langhammer, Tom VanCourt	FPGA Floating Point Datapath Compiler.	FCCM	2009	DBLP DOI BibTeX RDF	performance computing, optimization, FPGA, floating point
1	Kostas Theocharoulis, Charalampos Manifavas, Ioannis Papaefstathiou	High-End Reconfigurable Systems for Fast Windows' Password Cracking.	FCCM	2009	DBLP DOI BibTeX RDF	Security, FPGAs, Rainbow Tables
1	Siddhartha Datta, Parag Beeraka, Ron Sass	RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function.	FCCM	2009	DBLP DOI BibTeX RDF	BLASTn, FPGA
1	Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis	Optical Flow on the Ambric Massively Parallel Processor Array (MPPA).	FCCM	2009	DBLP DOI BibTeX RDF	MPPA, FPGA, Optical Flow, Reconfigurable Computing
1	Jason D. Bakos, Krishna K. Nagar	Exploiting Matrix Symmetry to Improve FPGA-Accelerated Conjugate Gradient.	FCCM	2009	DBLP DOI BibTeX RDF	sparse matrix vector multiply, FPGA, high-performance computing, reconfigurable computing, conjugate gradient
1	Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser	Generic Software Framework for Adaptive Applications on FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	field-programmable gate arrays, adaptive systems, dynamic reconfiguration, software defined radio
1	Jason Cong, Karthik Gururaj, Bin Liu 0006, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou	Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization.	FCCM	2009	DBLP DOI BibTeX RDF	precision analysis, static analysis, bitwidth
1	Volodymyr V. Kindratenko, Robert J. Brunner	Accelerating Cosmological Data Analysis with FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	two-point angular correlation, reconfigurable computing
1	Andrew W. H. House, Paul Chow	Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems.	FCCM	2008	DBLP DOI BibTeX RDF
1	Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass	FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
1	Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan	Scaling Soft Processor Systems.	FCCM	2008	DBLP DOI BibTeX RDF
1	John Curreri, Seth Koehler, Brian Holland, Alan D. George	Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing.	FCCM	2008	DBLP DOI BibTeX RDF
1	Hayden Kwok-Hay So, Robert W. Brodersen	Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH.	FCCM	2008	DBLP DOI BibTeX RDF
1	Antonis Nikitakis, Ioannis Papaefstathiou	A Memory-Efficient FPGA-based Classification Engine.	FCCM	2008	DBLP DOI BibTeX RDF
1	Sven-Ole Voigt, Thomas Teufel	Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms.	FCCM	2008	DBLP DOI BibTeX RDF
1	Kimmo U. Järvinen, Jorma O. Skyttä	High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves.	FCCM	2008	DBLP DOI BibTeX RDF
1	Miad Faezipour, Mehrdad Nourani	Reconfigurable Constraint Repetition Unit for Regular Expression Matching.	FCCM	2008	DBLP DOI BibTeX RDF
1	Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman	An Extensible I/O Subsystem.	FCCM	2008	DBLP DOI BibTeX RDF
1	David DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor Davenport, Steve Poole 0001	An Implementation of the Conjugate Gradient Algorithm on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
1	Hoang Le, Weirong Jiang, Viktor K. Prasanna	A SRAM-based Architecture for Trie-based IP Lookup Using FPGA.	FCCM	2008	DBLP DOI BibTeX RDF
1	Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, Raj Shekhar	Multiobjective Optimization of FPGA-Based Medical Image Registration.	FCCM	2008	DBLP DOI BibTeX RDF
1	Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker 0001	Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.	FCCM	2008	DBLP DOI BibTeX RDF
1	Konstantinos Papadopoulos 0003, Ioannis Papaefstathiou	Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor.	FCCM	2008	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk	Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation.	FCCM	2008	DBLP DOI BibTeX RDF
1	Michael Butts, Brad Budlong, Paul Wasson, Ed White	Reconfigurable Work Farms on a Massively Parallel Processor Array.	FCCM	2008	DBLP DOI BibTeX RDF
1	Jonathan Bachrach, Dany Qumsiyeh, Mark M. Tobenkin	Hardware Scripting in Gel.	FCCM	2008	DBLP DOI BibTeX RDF
1	Sherman Braganza, Miriam Leeser	An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware.	FCCM	2008	DBLP DOI BibTeX RDF
1	Shannon Koh, Oliver Diessel	The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration.	FCCM	2008	DBLP DOI BibTeX RDF
1	Kenneth L. Pocek, Duncan A. Buell (eds.)	16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA	FCCM	2008	DBLP BibTeX RDF
1	Dirk Koch, Christian Haubelt, Jürgen Teich	Efficient Reconfigurable On-Chip Buses for FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
1	Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan, Philip Heng Wai Leong	Map-reduce as a Programming Model for Custom Computing Machines.	FCCM	2008	DBLP DOI BibTeX RDF
1	Hanyu Liu, Xiaolei Chen, Yajun Ha	An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects.	FCCM	2008	DBLP DOI BibTeX RDF
1	Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen	A Hardware Efficient Support Vector Machine Architecture for FPGA.	FCCM	2008	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass	Reconfigurable Computing Cluster Project: Phase I Brief.	FCCM	2008	DBLP DOI BibTeX RDF
1	Jack Coyne, David Cyganski, R. James Duckworth	FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography.	FCCM	2008	DBLP DOI BibTeX RDF
1	Emilio Castillo, César Pedraza, Javier Castillo, Cristobal Camarero, José Luis Bosque, Rafael Menéndez de Llano, José Ignacio Martínez	SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable Hardware.	FCCM	2008	DBLP DOI BibTeX RDF
1	Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding, Harold W. Carter	Fast Multivariate Signature Generation in Hardware: The Case of Rainbow.	FCCM	2008	DBLP DOI BibTeX RDF
1	Mary Ellen Fuess, Miriam Leeser, Tim Leonard	An FPGA Implementation of Explicit-State Model Checking.	FCCM	2008	DBLP DOI BibTeX RDF
1	David DuBois, Andrew DuBois, Carolyn Connor Davenport, Steve Poole 0001	Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer.	FCCM	2008	DBLP DOI BibTeX RDF
1	Karthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George	Scalable and Portable Architecture for Probability Density Function Estimation on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.	FCCM	2008	DBLP DOI BibTeX RDF
1	Saar Drimer, Tim Güneysu, Christof Paar	DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
1	Ling Zhuo, Qingbo Wang, Viktor K. Prasanna	Matrix Computations on Heterogeneous Reconfigurable Systems.	FCCM	2008	DBLP DOI BibTeX RDF
1	Jeff Chase, Brent E. Nelson, John Bodily, Zhaoyi Wei, Dah-Jye Lee	Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study.	FCCM	2008	DBLP DOI BibTeX RDF
1	Andrew J. Wong, Warren J. Gross	Configurable Flow Models for FPGA Particle Graphics Engines.	FCCM	2008	DBLP DOI BibTeX RDF
1	François Charot, Christophe Wolinski, Nicolas Fau, François Hamon	A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture.	FCCM	2008	DBLP DOI BibTeX RDF
1	Kenneth Eguro, Scott Hauck	Simultaneous Retiming and Placement for Pipelined Netlists.	FCCM	2008	DBLP DOI BibTeX RDF
1	Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi	Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding.	FCCM	2008	DBLP DOI BibTeX RDF
1	Karl Meier, Alessandro Forin	Hardware Compilation from Machine Code with M2V.	FCCM	2008	DBLP DOI BibTeX RDF
1	Jason Wu, John Williams 0004, Neil W. Bergmann	System Level Design Methodology for Hybrid Multi-Processor SoC on FPGA.	FCCM	2008	DBLP DOI BibTeX RDF
1	Hangpei Tian, Deyuan Gao, Wu Wei, Xiaoya Fan, Yian Zhu	Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion.	FCCM	2008	DBLP DOI BibTeX RDF
1	Georgios-Grigorios Mplemenos, Ioannis Papaefstathiou	MPLEM: An 80-processor FPGA Based Multiprocessor System.	FCCM	2008	DBLP DOI BibTeX RDF
1	Edward Chen, William A. Gruver, Dorian Sabaz, Lesley Shannon	Facilitating Processor-Based DPR Systems for non-DPR Experts.	FCCM	2008	DBLP DOI BibTeX RDF
1	Martin C. Herbordt, Francois Kosie, Josh Model	An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular Dynamics.	FCCM	2008	DBLP DOI BibTeX RDF
1	William George Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer	Power-Aware and Branch-Aware Word-Length Optimization.	FCCM	2008	DBLP DOI BibTeX RDF
1	Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese	A Scalable High Throughput Firewall in FPGA.	FCCM	2008	DBLP DOI BibTeX RDF
1	David J. Greaves, Satnam Singh	Kiwi: Synthesis of FPGA Circuits from Parallel Programs.	FCCM	2008	DBLP DOI BibTeX RDF
1	Wenyin Fu, Katherine Compton	Scheduling Intervals for Reconfigurable Computing.	FCCM	2008	DBLP DOI BibTeX RDF
1	Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan	ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.	FCCM	2008	DBLP DOI BibTeX RDF
1	Matthew French, Erik K. Anderson, Dong-In Kang	Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration.	FCCM	2008	DBLP DOI BibTeX RDF
1	Wanda Gay, Clay S. Gloster Jr.	A Configurable Processor Synthesis System.	FCCM	2007	DBLP DOI BibTeX RDF
1	Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Tobias Becker, Wayne Luk, Peter Y. K. Cheung	Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration.	FCCM	2007	DBLP DOI BibTeX RDF
1	Khaled Benkrid, Ying Liu 0003, Abdsamad Benkrid	Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment.	FCCM	2007	DBLP DOI BibTeX RDF
1	Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan	Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures.	FCCM	2007	DBLP DOI BibTeX RDF
1	Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo	PixelStreams-based implementation of videodetector.	FCCM	2007	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Heterogeneous Floorplanner for FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
1	Zachary K. Baker, Maya B. Gokhale, Justin L. Tripp	Matched Filter Computation on FPGA, Cell and GPU.	FCCM	2007	DBLP DOI BibTeX RDF

Publications at "FCCM"( http://dblp.L3S.de/Venues/FCCM )