Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani |
Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Wendi Wang, Bo Duan, Wen Tang, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui Sun |
A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yupeng Chen, Bertil Schmidt, Douglas L. Maskell |
Accelerating short read mapping on an FPGA (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Vincent Mirian, Paul Chow |
FCache: a system for cache coherent processing on FPGAs. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang |
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Robin Panda, Scott Hauck |
Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai |
A novel full coverage test method for CLBs in FPGA (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yi-Hua E. Yang, Oguzhan Erdem, Viktor K. Prasanna |
Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So |
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | S. Alexander Chin, Paul Chow |
OpenCL memory infrastructure for FPGAs (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jesus Savage, Rodrigo Savage, Marco Morales-Aguirre, Ángel Fernando Kuri Morales |
Adaptive FPGA-based robotics state machine architecture derived with genetic algorithms (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Nathaniel H. Rollins, Michael J. Wirthlin |
Reliability of a softcore processor in a commercial SRAM-based FPGA. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Haoran Li, Youn Sung Park, Zhengya Zhang |
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Warren Wai-Kit Shum, Jason Helge Anderson |
Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jason Cong, Bingjun Xiao |
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Masahiro Fujita, Hiroaki Yoshida |
Post-silicon debugging targeting electrical errors with patchable controllers (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | John Curreri, Greg Stitt, Alan D. George |
Communication visualization for bottleneck detection of high-level synthesis applications. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Chris C. Wang, Guy G. F. Lemieux |
Parallel FPGA placement based on individual LUT placement (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Declan Walsh, Piotr Dudek |
A field programmable array core for image processing (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Nikil Mehta, Raphael Rubin, André DeHon |
Limit study of energy & delay benefits of component-specific routing. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Charles Eric LaForest, John Gregory Steffan |
OCTAVO: an FPGA-centric processor family. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Qinghong Wu, Kenneth S. McElvain |
A fast discrete placement algorithm for FPGAs. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Assem A. M. Bsoul, Steven J. E. Wilton |
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk |
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Lingkan Gong, Oliver Diessel |
Functionally verifying state saving and restoration in dynamically reconfigurable systems. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jianwen Chen, Jason Cong, Ming Yan 0006, Yi Zou |
FPGA-accelerated 3D reconstruction using compressive sensing. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jeremy Fowers, Greg Brown, Patrick Cooke, Greg Stitt |
A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Samuel Bayliss, George A. Constantinides |
Optimizing SDRAM bandwidth for custom FPGA loop accelerators. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas |
A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Chih-Hsun Chou, Fong Pong, Nian-Feng Tzeng |
Speedy FPGA-based packet classifiers with low on-chip memory requirements. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Anh-Tuan Hoang, Takeshi Fujino |
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad |
Efficient in-system RTL verification and debugging using FPGAs (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings |
EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai |
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Katherine Compton, Brad L. Hutchings (eds.) |
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, FPGA 2012, Monterey, California, USA, February 22-24, 2012 |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | André Seffrin, Sorin A. Huss |
Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Michael Papamichael, James C. Hoe |
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne |
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Zefu Dai, Jianwen Zhu |
Saturating the transceiver bandwidth: switch fabric design on FPGAs. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Wei Ting Loke, Yajun Ha |
Power-aware FPGA technology mapping for programmable-VT architectures (abstract only). |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jason Cong, Yi Zou |
Resolving implicit barrier synchronizations in FPGA HLS (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Lu Zhang 0018, Ke Zhang 0012, Tian Sheuan Chang, Gauthier Lafruit, Georgi Krasimirov Kuzmanov, Diederik Verkest |
Real-time high-definition stereo matching on FPGA. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Haohuan Fu, Robert G. Clapp |
Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | David Grant, Chris C. Wang, Guy G. Lemieux |
A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | John Wawrzynek, Katherine Compton (eds.) |
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011 |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Chris C. Wang, Guy G. Lemieux |
Scalable and deterministic timing-driven parallel placement for FPGAs. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Satnam Singh |
The RLOC is dead - long live the RLOC. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis |
High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk |
A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Juergen Ributzka, Yuhei Hayashi, Fei Chen, Guang R. Gao |
DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Mingjie Lin, Shaoyi Cheng, John Wawrzynek |
Using many-core architectural templates for FPGA-based computing (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Tim Papenfuss, Holger Michel |
A platform for high level synthesis of memory-intensive image processing algorithms. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Alfio Lombardo, Diego Reforgiato Recupero, Giovanni Schembra |
An accelerated and energy-efficient traffic monitor using the NetFPGA (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li 0003, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner |
A 65nm flash-based FPGA fabric optimized for low cost and power. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hossein Omidian Savarbaghi, Kia Bazargan |
FPGA placement by graph isomorphism (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jason Luu, Jason Helge Anderson, Jonathan Rose |
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Somnath Paul, Swarup Bhunia |
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan |
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Raphael Rubin, André DeHon |
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev |
Variation tolerant asynchronous FPGA (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Scott Y. L. Chin, Steven J. E. Wilton |
Towards scalable FPGA CAD through architecture. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Andrew W. Hill, Andrea Di Blas, Richard Hughey |
FPGA-based fine-grain parallel computing (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hoang Le, Thilan Ganegedara, Viktor K. Prasanna |
Memory-efficient and scalable virtual routers using FPGA. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yu Cai 0001, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai |
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Andrei Hagiescu, Weng-Fai Wong |
Co-synthesis of FPGA-based application-specific floating point simd accelerators. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ji Sun, Ray Bittner, Ken Eguro |
FPGA side-channel receivers. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Fadi Obeidat, Robert H. Klenke |
Microblaze: an application-independent fpga-based profiler (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ling Liu, Oleksii Morozov, Yuxing Han 0001, Jürg Gutknecht, Patrick R. Hunziker |
Automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne |
Reducing the pressure on routing resources of FPGAs with generic logic chains. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong |
A monte-carlo floating-point unit for self-validating arithmetic. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Dirk Koch, Jim Tørresen |
FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Trung Hieu Bui, Tuan Duy Anh Nguyen, Ngoc Thinh Tran |
BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Haile Yu, Qiang Xu 0001, Philip Heng Wai Leong |
On timing yield improvement for FPGA designs using architectural symmetry (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Doris Chen, Deshanand P. Singh |
Line-level incremental resynthesis techniques for FPGAs. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer |
Leap scratchpads: automatic memory and cache management for reconfigurable logic. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jianfeng Zhu 0001, Dong Wu, Yaru Yan, Xiao Yu, Hu He 0001, Liyang Pan |
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jonathan Rose, Guy G. Lemieux |
The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan |
A streaming FPGA implementation of a steerable filter for real-time applications (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Charles Lo, Paul Chow |
Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek |
Bridging the GPGPU-FPGA efficiency gap. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Martin Labrecque, J. Gregory Steffan |
NetTM: faster and easier synchronization for soft multicores via transactional memory. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Henry Wong, Vaughn Betz, Jonathan Rose |
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Abdullah Nazma Nowroz, Sherief Reda |
Thermal and power characterization of field-programmable gate arrays. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He 0001 |
Fault modeling and characteristics of SRAM-based FPGAs (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski |
LegUp: high-level synthesis for FPGA-based processor/accelerator systems. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Tobias Kenter, Christian Plessl, Marco Platzner, Michael Kauschke |
Performance estimation framework for automated exploration of CPU-accelerator architectures. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux |
VEGAS: soft vector processor with scratchpad memory. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Justin S. J. Wong, Peter Y. K. Cheung |
Improved delay measurement method in FPGA based on transition probability. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck |
Energy-efficient specialization of functional units in a coarse-grained reconfigurable array. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ravikesh Chandra, Oliver Sinnen |
Towards automated optimisation of tool-generated HW/SW sopc designs (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Neil Steiner, Aaron Wood, Hamid Shojaei, Jacob Couch, Peter Athanas, Matthew French |
Torc: towards an open-source tool flow. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Steve Richfield |
Dealing with the "itanium effect" (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Abhay Tavaragiri, Jacob Couch, Peter Athanas |
Exploration of FPGA interconnect for the design of unconventional antennas. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Schinke, Wallace Shep Pitts, Neil Di Spigna, Paul D. Franzon |
Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Xun Chen, Jianwen Zhu |
Regular fabric for regular FPGA (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | John Wawrzynek |
Should the academic community launch an open-source FPGA device and tools effort?: evening panel. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Qiang Gao, Robert W. Stewart |
Improved double angle complex rotation QRD-RLS. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Peter Grossmann, Miriam Leeser |
A prototype FPGA for subthreshold-optimized CMOS (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Steven Trimberger, Jason Moore, Weiguang Lu |
Authenticated encryption for FPGA bitstreams. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|