Search results for "FinFET"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Aoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha	Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
14	Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar	Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
14	Abdullah Guler, Niraj K. Jha	Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
14	Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan	Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
14	Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta	Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
14	C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi	A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
14	Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric	ASAP7: A 7-nm finFET predictive process design kit.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
14	Shashank Dubey, Pravin Neminath Kondekar	Performance comparison of conventional and strained FinFET inverters.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
14	Po-Hsun Wu, Mark Po-Hung Lin, Xin Li 0001, Tsung-Yi Ho	Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
14	Kolsoom Mehrabi, Behzad Ebrahimi, Roohollah Yarmand, Ali Afzali-Kusha, Hamid Mahmoodi	Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
14	Arka Dutta, Kalyan Koley, Samar K. Saha, Chandan Kumar Sarkar	Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
14	Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung	Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
14	Debajit Bhattacharya, Niraj K. Jha	Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
14	Yu Yuan, Erdal Oruklu	Leakage reduction techniques for FinFET datapath circuits.	EIT	2016	DBLP DOI BibTeX RDF
14	Jiwanjot Kahlon, Pradeep Kumar 0006, Anubhav Garg, Ashutosh Gupta 0002	Low power and temperature compatible FinFET based full adder circuit with optimised area.	ICACCI	2016	DBLP DOI BibTeX RDF
14	Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean	Towards high performance sub-10nm finW bulk FinFET technology.	ESSDERC	2016	DBLP DOI BibTeX RDF
14	Erick Garcia Cordero, Hoel Guerin, Amira Muhech, Francesco Bellando, Adrian M. Ionescu	Heterogeneous integration of low power pH FinFET sensors with passive capillary microfluidics and miniaturized Ag/AgCl quasi-Reference Electrode.	ESSDERC	2016	DBLP DOI BibTeX RDF
14	Santosh Koppa, Paromita Syam, Sruthi Nanduru, Eugene John	A quantitative performance analysis of FinFET based multiplier circuits.	MWSCAS	2016	DBLP DOI BibTeX RDF
14	Mahmoud Darwich, Ahmed Abdelgawad 0001, Magdy A. Bayoumi	A Survey on the power and robustness of FinFET SRAM.	MWSCAS	2016	DBLP DOI BibTeX RDF
14	James Karp, Michael J. Hart, Mohammed Fakhruddin, Vassili Kireev, Larry Horwitz, Matthew Hogan	FinFET MPSoC 32 Gb/s transceivers: Custom ESD protection and verification.	MWSCAS	2016	DBLP DOI BibTeX RDF
14	Mohamed Mohie El-Din, Hossam A. H. Fahmy, Yehea Ismail, Noha Gamal, Hassan Mostafa	Leakage power evaluation of FinFET-based FPGA cluster under threshold voltage variation.	IDT	2016	DBLP DOI BibTeX RDF
14	Eslam Amr, Marina Maher, Amir Rashad, Mohamed Raafat, Yosif Diaa, Eslam Yahya, Yehea Ismail	Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology.	ICM	2016	DBLP DOI BibTeX RDF
14	Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz	On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs.	ISVLSI	2016	DBLP DOI BibTeX RDF
14	Andrew Whetzel, Mircea R. Stan	Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits.	ISVLSI	2016	DBLP DOI BibTeX RDF
14	Magnanil Goswami	Geometric Programming: Chaperoning the Optimization of Symmetric FinFET Circuits.	SoCPaR	2016	DBLP DOI BibTeX RDF
14	Luke England, Sukeshwar Kannan, Rahul Agarwal, Daniel Smith	Impact of TSV integration on 14nm FinFET device performance.	3DIC	2016	DBLP DOI BibTeX RDF
14	Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac	Behavior and test of open-gate defects in FinFET based cells.	ETS	2016	DBLP DOI BibTeX RDF
14	Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas	Performance evaluation of optimized transistor networks built using independent-gate FinFET.	LASCAS	2016	DBLP DOI BibTeX RDF
14	Alexandra L. Zimpeck, Ricardo Reis 0001	Impact of variability effects on FinFET transistors and combinational cells.	ICECS	2016	DBLP DOI BibTeX RDF
14	Fábio G. R. G. da Silva, Paulo F. Butzen, Cristina Meinhardt	PVT variability analysis of FinFET and CMOS XOR circuits at 16nm.	ICECS	2016	DBLP DOI BibTeX RDF
14	Devansh Sinha, Shyam Akashe	Design of low power 3-bit TIQ based ADC by using FinFET Technology.	ICTCS	2016	DBLP DOI BibTeX RDF
14	Ajay Kumar Dadoria, Kavita Khare, R. P. Singh	Leakage Power Reduction Technique by using FinFET Technology.	ICTCS	2016	DBLP DOI BibTeX RDF
14	Jainendra Tripathi, Ranjeet Singh Tomar, Shyam Akashe	A SDDG FinFET Based Op Amp with DSB Circuit.	ICTCS	2016	DBLP DOI BibTeX RDF
14	Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee	A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology.	ESSCIRC	2016	DBLP DOI BibTeX RDF
14	Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto 0001, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang	A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET.	ESSCIRC	2016	DBLP DOI BibTeX RDF
14	Girish Pahwa, Tapas Dutta, Amit Agarwal 0007, Yogesh Singh Chauhan	Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.	ESSCIRC	2016	DBLP DOI BibTeX RDF
14	Ermao Cai, Dimitrios Stamoulis, Diana Marculescu	Exploring aging deceleration in FinFET-based multi-core systems.	ICCAD	2016	DBLP DOI BibTeX RDF
14	Warin Sootkaneung, Pipatphon Lapamonpinyo, Sasithorn Chookaew, Suppachai Howimanporn	NBTI in FinFET Circuits under the Temperature Effect Inversion.	CSE/EUC/DCABES	2016	DBLP DOI BibTeX RDF
14	Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl	23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path.	ISSCC	2016	DBLP DOI BibTeX RDF
14	Taejoong Song, Woojin Rim, Sunghyun Park 0003, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi 0001, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyu-Hong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, E. S. Jung, Steve Sungho Park, Kinam Kim	17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization.	ISSCC	2016	DBLP DOI BibTeX RDF
14	Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita	4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.	ISSCC	2016	DBLP DOI BibTeX RDF
14	John Keane 0001, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang 0001	17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.	ISSCC	2016	DBLP DOI BibTeX RDF
14	Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang	3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET.	ISSCC	2016	DBLP DOI BibTeX RDF
14	John M. Wilson 0002, Matthew R. Fojtik, John W. Poulton, Xi Chen 0033, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally	8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.	ISSCC	2016	DBLP DOI BibTeX RDF
14	Mayank Raj, Parag Upadhyaya, Yohan Frans, Ken Chang	A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
14	Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken	A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
14	Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen 0001, Augusto Ronchini Ximenes, Robert Bogdan Staszewski	A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
14	Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii	A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
14	Parag Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, Jay Im, Junho Cho, Kee Hian Tan, Scott McLeod, Stanley Chen, Wenfeng Zhang, Yohan Frans, Ken Chang	A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
14	Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang 0002, Ken Chang	A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
14	Ravi Patel 0001, Eby G. Friedman, Praveen Raghavan	Power noise in 14, 10, and 7 nm FinFET CMOS technologies.	ISCAS	2016	DBLP DOI BibTeX RDF
14	Leila Bagheriye, Roghayeh Saeidi, Siroos Toofan	Low power and roboust FinFET SRAM cell using independent gate control.	ISCAS	2016	DBLP DOI BibTeX RDF
14	Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Augusto da Luz Reis	FinFET cells with different transistor sizing techniques against PVT variations.	ISCAS	2016	DBLP DOI BibTeX RDF
14	Motoi Ichihashi, Jia Zeng, Cole Zemke, Irene Lin, Greg Northrop, Ning Jin, Jongwook Kye	Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology.	SoCC	2016	DBLP DOI BibTeX RDF
14	Hyosig Won, Katsuhiro Shimazu	Statistical design attribute identification for FinFET outlier and Silicon-to-SPICE gap.	SoCC	2016	DBLP DOI BibTeX RDF
14	Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell	Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect.	LATS	2016	DBLP DOI BibTeX RDF
14	Ravi Patel 0001, Kan Xu, Eby G. Friedman, Praveen Raghavan	Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF
14	C. Anju, Nisha Kuruvilla, T. E. Ayoob Khan, T. A. Shahul Hameed	Performance Analysis of Wavy FinFET and Optimization for Leakage Reduction.	iNIS	2016	DBLP DOI BibTeX RDF
14	Vivek Kumar, Vikas Mahor, Manisha Pattanaik	Novel Ultra Low Leakage FinFET Based SRAM Cell.	iNIS	2016	DBLP DOI BibTeX RDF
14	Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik	FinFET-Based Low Power Address Decoder under Process Variation.	iNIS	2016	DBLP DOI BibTeX RDF
14	Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik	Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell.	iNIS	2016	DBLP DOI BibTeX RDF
14	Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos	Novel FinFET Based Physical Unclonable Functions for Efficient Security Integration in the IoT.	iNIS	2016	DBLP DOI BibTeX RDF
14	Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma	Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET.	iNIS	2016	DBLP DOI BibTeX RDF
14	Tiansong Cui, Ji Li 0006, Alireza Shafaei, Shahin Nazarian, Massoud Pedram	An efficient timing analysis model for 6T FinFET SRAM using current-based method.	ISQED	2016	DBLP DOI BibTeX RDF
14	Rahaprian Mudiarasan Premavathi, Qiang Tong, Ken Choi, Yunsik Lee	A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability.	ISOCC	2016	DBLP DOI BibTeX RDF
14	Ashish Joshi, Thejaswani Putta, Tooraj Nikoubin	Power and Energy Efficient Standard Cell Library Design in CDM Logic Style with FinFET Transistors.	ICCCNT	2016	DBLP DOI BibTeX RDF
14	Jeong-Won Kim, Deok Keun Oh, Juho Kim	Performance optimization in FinFET-based circuit using TILOS-like gate sizing.	ISIC	2016	DBLP DOI BibTeX RDF
14	Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha	Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.	VLSID	2016	DBLP DOI BibTeX RDF
14	Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu	FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay.	VLSID	2016	DBLP DOI BibTeX RDF
14	S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad	FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices.	ICRC	2016	DBLP DOI BibTeX RDF
14	C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan	A robust 8T FinFET SRAM cell with improved stability for low voltage applications.	VDAT	2016	DBLP DOI BibTeX RDF
14	Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw	Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.	DAC	2016	DBLP DOI BibTeX RDF
14	Meng-Chou Chang, Siao-Siang Liu	FinFET-based TCAMs with matchline-accelerating sense amplifiers.	GCCE	2016	DBLP DOI BibTeX RDF
14	Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Yuan Xie 0001	Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.	IEEE Trans. Multi Scale Comput. Syst.	2015	DBLP DOI BibTeX RDF
14	Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park 0003, Yongho Kim, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi, Hyo-Sig Won, Jaehong Park	A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
14	Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang	A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
14	Ying Zhang 0016, Sui Chen, Lu Peng 0001, Shaoming Chen	NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity.	Integr.	2015	DBLP DOI BibTeX RDF
14	Guillaume Hubert, Laurent Artola, D. Regis	Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation.	Integr.	2015	DBLP DOI BibTeX RDF
14	Mohammad Ansari, Hassan Afzali-Kusha, Behzad Ebrahimi, Zainalabedin Navabi, Ali Afzali-Kusha, Massoud Pedram	A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.	Integr.	2015	DBLP DOI BibTeX RDF
14	Aoxiang Tang, Yang Yang, Chun-Yi Lee, Niraj K. Jha	McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
14	Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha	Design of Efficient Content Addressable Memories in High-Performance FinFET Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
14	Brad D. Gaynor, Soha Hassoun	Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
14	Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung	Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
14	Ting-Jung Lin, Wei Zhang 0012, Niraj K. Jha	FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
14	Tatsuya Ohguro, Satoshi Inaba, Akio Kaneko, Kimitoshi Okano	Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits.	IEICE Trans. Electron.	2015	DBLP DOI BibTeX RDF
14	Vikas Mahor, Manisha Pattanaik	Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
14	Alexander Korobkov, Amit Agarwal, Subramanian Venkateswaran	Efficient FinFET Device Model Implementation for SPICE Simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
14	Behzad Ebrahimi, Reza Asadpour, Ali Afzali-Kusha, Massoud Pedram	A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
14	Kaisheng Ma, Xiaoxin Cui, Kai Liao, Nan Liao, Di Wu, Dunshan Yu	Key characterization factors of accurate power modeling for FinFET circuits.	Sci. China Inf. Sci.	2015	DBLP DOI BibTeX RDF
14	Xianmin Chen, Niraj K. Jha	gem5-PVT: A Framework for FinFET System Simulation under PVT Variations.	ACM J. Emerg. Technol. Comput. Syst.	2015	DBLP DOI BibTeX RDF
14	Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin	FinFET-Based Low-Swing Clocking.	ACM J. Emerg. Technol. Comput. Syst.	2015	DBLP DOI BibTeX RDF
14	Vikas Mahor, Manisha Pattanaik	Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
14	Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma 0001	New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
14	Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001	Variability Influence on FinFET-Based On-Chip Memory Data Paths.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
14	K. P. Pradhan, Sushanta Kumar Mohapatra, Prasanna Kumar Sahu	Design Equivalent Scaling on Double Gate FinFET Towards Analog and RF Figures of Merits: A Technology Computer Aided Design Estimation.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
14	Pooja Joshi, Saurabh Khandelwal, Shyam Akashe	Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
14	Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Impact of PVT variability on 20 nm FinFET standard cells.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
14	Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma 0001	A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
14	Usman Khalid, Antonio Mastrandrea, Mauro Olivieri	Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
14	Ko-Chun Lee, Ming-Long Fan, Pin Su	Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF