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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 59 occurrences of 34 keywords
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Results
Found 1191 publication records. Showing 1191 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Aoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha |
Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(4), pp. 42:1-42:21, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar |
Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(4), pp. 36:1-36:12, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Abdullah Guler, Niraj K. Jha |
Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 13(2), pp. 26:1-26:25, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan |
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(4), pp. 38:1-38:23, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta |
Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 55, pp. 19-25, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi |
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 51, pp. 75-88, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric |
ASAP7: A 7-nm finFET predictive process design kit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 53, pp. 105-115, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Shashank Dubey, Pravin Neminath Kondekar |
Performance comparison of conventional and strained FinFET inverters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 55, pp. 108-115, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Po-Hsun Wu, Mark Po-Hung Lin, Xin Li 0001, Tsung-Yi Ho |
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 21(3), pp. 39:1-39:22, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Kolsoom Mehrabi, Behzad Ebrahimi, Roohollah Yarmand, Ali Afzali-Kusha, Hamid Mahmoodi |
Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 65, pp. 20-26, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Arka Dutta, Kalyan Koley, Samar K. Saha, Chandan Kumar Sarkar |
Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 61, pp. 99-105, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung |
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7), pp. 1023-1032, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Debajit Bhattacharya, Niraj K. Jha |
Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8), pp. 1176-1187, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Yu Yuan, Erdal Oruklu |
Leakage reduction techniques for FinFET datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2016 IEEE International Conference on Electro Information Technology, EIT 2016, Grand Forks, ND, USA, May 19-21, 2016, pp. 638-641, 2016, IEEE, 978-1-4673-9985-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Jiwanjot Kahlon, Pradeep Kumar 0006, Anubhav Garg, Ashutosh Gupta 0002 |
Low power and temperature compatible FinFET based full adder circuit with optimised area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2016 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2016, Jaipur, India, September 21-24, 2016, pp. 2121-2125, 2016, IEEE, 978-1-5090-2029-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean |
Towards high performance sub-10nm finW bulk FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, September 12-15, 2016, pp. 131-134, 2016, IEEE, 978-1-5090-2969-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Erick Garcia Cordero, Hoel Guerin, Amira Muhech, Francesco Bellando, Adrian M. Ionescu |
Heterogeneous integration of low power pH FinFET sensors with passive capillary microfluidics and miniaturized Ag/AgCl quasi-Reference Electrode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, September 12-15, 2016, pp. 452-455, 2016, IEEE, 978-1-5090-2969-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Santosh Koppa, Paromita Syam, Sruthi Nanduru, Eugene John |
A quantitative performance analysis of FinFET based multiplier circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Mahmoud Darwich, Ahmed Abdelgawad 0001, Magdy A. Bayoumi |
A Survey on the power and robustness of FinFET SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | James Karp, Michael J. Hart, Mohammed Fakhruddin, Vassili Kireev, Larry Horwitz, Matthew Hogan |
FinFET MPSoC 32 Gb/s transceivers: Custom ESD protection and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Mohamed Mohie El-Din, Hossam A. H. Fahmy, Yehea Ismail, Noha Gamal, Hassan Mostafa |
Leakage power evaluation of FinFET-based FPGA cluster under threshold voltage variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 11th International Design & Test Symposium, IDT 2016, Hammamet, Tunisia, December 18-20, 2016, pp. 137-141, 2016, IEEE, 978-1-5090-4900-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Eslam Amr, Marina Maher, Amir Rashad, Mohamed Raafat, Yosif Diaa, Eslam Yahya, Yehea Ismail |
Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 28th International Conference on Microelectronics, ICM 2016, Giza, Egypt, December 17-20, 2016, pp. 325-328, 2016, IEEE, 978-1-5090-5721-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz |
On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 449-454, 2016, IEEE Computer Society, 978-1-4673-9039-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Andrew Whetzel, Mircea R. Stan |
Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 467-472, 2016, IEEE Computer Society, 978-1-4673-9039-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Magnanil Goswami |
Geometric Programming: Chaperoning the Optimization of Symmetric FinFET Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCPaR ![In: Proceedings of the Eighth International Conference on Soft Computing and Pattern Recognition, SoCPaR 2016, Vellore, India, December 19-21, 2016, pp. 193-202, 2016, Springer, 978-3-319-60617-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Luke England, Sukeshwar Kannan, Rahul Agarwal, Daniel Smith |
Impact of TSV integration on 14nm FinFET device performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016, San Francisco, CA, USA, November 8-11, 2016, pp. 1-5, 2016, IEEE, 978-1-5090-1399-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac |
Behavior and test of open-gate defects in FinFET based cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, pp. 1-6, 2016, IEEE, 978-1-4673-9659-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas |
Performance evaluation of optimized transistor networks built using independent-gate FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 7th Latin American Symposium on Circuits & Systems, LASCAS 2016, Florianopolis, Brazil, February 28 - March 2, 2016, pp. 227-230, 2016, IEEE, 978-1-4673-7835-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Alexandra L. Zimpeck, Ricardo Reis 0001 |
Impact of variability effects on FinFET transistors and combinational cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 440-441, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Fábio G. R. G. da Silva, Paulo F. Butzen, Cristina Meinhardt |
PVT variability analysis of FinFET and CMOS XOR circuits at 16nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 528-531, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Devansh Sinha, Shyam Akashe |
Design of low power 3-bit TIQ based ADC by using FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTCS ![In: ICTCS, pp. 95:1-95:4, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Ajay Kumar Dadoria, Kavita Khare, R. P. Singh |
Leakage Power Reduction Technique by using FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTCS ![In: ICTCS, pp. 15:1-15:5, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Jainendra Tripathi, Ranjeet Singh Tomar, Shyam Akashe |
A SDDG FinFET Based Op Amp with DSB Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTCS ![In: ICTCS, pp. 98:1-98:5, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee |
A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 461-464, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto 0001, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang |
A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 297-300, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Girish Pahwa, Tapas Dutta, Amit Agarwal 0007, Yogesh Singh Chauhan |
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 49-54, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Ermao Cai, Dimitrios Stamoulis, Diana Marculescu |
Exploring aging deceleration in FinFET-based multi-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016, pp. 111, 2016, ACM, 978-1-4503-4466-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Warin Sootkaneung, Pipatphon Lapamonpinyo, Sasithorn Chookaew, Suppachai Howimanporn |
NBTI in FinFET Circuits under the Temperature Effect Inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE/EUC/DCABES ![In: 2016 IEEE Intl Conference on Computational Science and Engineering, CSE 2016, and IEEE Intl Conference on Embedded and Ubiquitous Computing, EUC 2016, and 15th Intl Symposium on Distributed Computing and Applications for Business Engineering, DCABES 2016, Paris, France, August 24-26, 2016, pp. 343-350, 2016, IEEE Computer Society, 978-1-5090-3593-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl |
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 408-409, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Taejoong Song, Woojin Rim, Sunghyun Park 0003, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi 0001, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyu-Hong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, E. S. Jung, Steve Sungho Park, Kinam Kim |
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 306-307, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita |
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 80-81, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | John Keane 0001, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang 0001 |
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 308-309, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang |
3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 68-70, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | John M. Wilson 0002, Matthew R. Fojtik, John W. Poulton, Xi Chen 0033, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally |
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 156-157, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Mayank Raj, Parag Upadhyaya, Yohan Frans, Ken Chang |
A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken |
A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen 0001, Augusto Ronchini Ximenes, Robert Bogdan Staszewski |
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii |
A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Parag Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, Jay Im, Junho Cho, Kee Hian Tan, Scott McLeod, Stanley Chen, Wenfeng Zhang, Yohan Frans, Ken Chang |
A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang 0002, Ken Chang |
A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Ravi Patel 0001, Eby G. Friedman, Praveen Raghavan |
Power noise in 14, 10, and 7 nm FinFET CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 37-40, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Leila Bagheriye, Roghayeh Saeidi, Siroos Toofan |
Low power and roboust FinFET SRAM cell using independent gate control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 49-52, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Augusto da Luz Reis |
FinFET cells with different transistor sizing techniques against PVT variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 45-48, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Motoi Ichihashi, Jia Zeng, Cole Zemke, Irene Lin, Greg Northrop, Ning Jin, Jongwook Kye |
Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016, pp. 271-274, 2016, IEEE, 978-1-5090-1367-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Hyosig Won, Katsuhiro Shimazu |
Statistical design attribute identification for FinFET outlier and Silicon-to-SPICE gap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016, pp. 35-40, 2016, IEEE, 978-1-5090-1367-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell |
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 17th Latin-American Test Symposium, LATS 2016, Foz do Iguacu, Brazil, April 6-8, 2016, pp. 129-134, 2016, IEEE, 978-1-5090-1331-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Ravi Patel 0001, Kan Xu, Eby G. Friedman, Praveen Raghavan |
Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016, pp. 233-238, 2016, ACM, 978-1-4503-4274-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | C. Anju, Nisha Kuruvilla, T. E. Ayoob Khan, T. A. Shahul Hameed |
Performance Analysis of Wavy FinFET and Optimization for Leakage Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 83-88, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Vivek Kumar, Vikas Mahor, Manisha Pattanaik |
Novel Ultra Low Leakage FinFET Based SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 89-92, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik |
FinFET-Based Low Power Address Decoder under Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 274-277, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik |
Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 268-273, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos |
Novel FinFET Based Physical Unclonable Functions for Efficient Security Integration in the IoT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 172-177, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma |
Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 264-267, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Tiansong Cui, Ji Li 0006, Alireza Shafaei, Shahin Nazarian, Massoud Pedram |
An efficient timing analysis model for 6T FinFET SRAM using current-based method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, CA, USA, March 15-16, 2016, pp. 263-268, 2016, IEEE, 978-1-5090-1213-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Rahaprian Mudiarasan Premavathi, Qiang Tong, Ken Choi, Yunsik Lee |
A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016, pp. 311-312, 2016, IEEE, 978-1-5090-3219-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Ashish Joshi, Thejaswani Putta, Tooraj Nikoubin |
Power and Energy Efficient Standard Cell Library Design in CDM Logic Style with FinFET Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, ICCCNT 2016, Dallas, TX, USA, July 6-8, 2016, pp. 12:1-12:5, 2016, ACM, 978-1-4503-4179-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Jeong-Won Kim, Deok Keun Oh, Juho Kim |
Performance optimization in FinFET-based circuit using TILOS-like gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIC ![In: International Symposium on Integrated Circuits, ISIC 2016, Singapore, December 12-14, 2016, pp. 1-4, 2016, IEEE, 978-1-4673-9019-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha |
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016, pp. 300-305, 2016, IEEE Computer Society, 978-1-4673-8700-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu |
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016, pp. 288-293, 2016, IEEE Computer Society, 978-1-4673-8700-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad |
FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRC ![In: IEEE International Conference on Rebooting Computing, ICRC 2016, San Diego, CA, USA, October 17-19, 2016, pp. 1-8, 2016, IEEE Computer Society, 978-1-5090-1370-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan |
A robust 8T FinFET SRAM cell with improved stability for low voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-1422-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw |
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016, pp. 76:1-76:6, 2016, ACM, 978-1-4503-4236-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Meng-Chou Chang, Siao-Siang Liu |
FinFET-based TCAMs with matchline-accelerating sense amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCCE ![In: IEEE 5th Global Conference on Consumer Electronics, GCCE 2016, Kyoto, Japan, October 11-14, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-2333-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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14 | Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Yuan Xie 0001 |
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multi Scale Comput. Syst. ![In: IEEE Trans. Multi Scale Comput. Syst. 1(4), pp. 195-206, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park 0003, Yongho Kim, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi, Hyo-Sig Won, Jaehong Park |
A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 158-169, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang |
A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 170-177, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Ying Zhang 0016, Sui Chen, Lu Peng 0001, Shaoming Chen |
NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 51, pp. 10-20, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Guillaume Hubert, Laurent Artola, D. Regis |
Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 50, pp. 39-47, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Mohammad Ansari, Hassan Afzali-Kusha, Behzad Ebrahimi, Zainalabedin Navabi, Ali Afzali-Kusha, Massoud Pedram |
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 50, pp. 91-106, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Aoxiang Tang, Yang Yang, Chun-Yi Lee, Niraj K. Jha |
McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(9), pp. 1616-1627, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha |
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(5), pp. 963-967, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Brad D. Gaynor, Soha Hassoun |
Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(8), pp. 1499-1507, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung |
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(11), pp. 2748-2752, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Ting-Jung Lin, Wei Zhang 0012, Niraj K. Jha |
FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(10), pp. 1987-2000, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Tatsuya Ohguro, Satoshi Inaba, Akio Kaneko, Kimitoshi Okano |
Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 98-C(6), pp. 455-460, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Vikas Mahor, Manisha Pattanaik |
Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(5), pp. 1550073:1-1550073:20, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Alexander Korobkov, Amit Agarwal, Subramanian Venkateswaran |
Efficient FinFET Device Model Implementation for SPICE Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10), pp. 1696-1699, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Behzad Ebrahimi, Reza Asadpour, Ali Afzali-Kusha, Massoud Pedram |
A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 43(12), pp. 2011-2024, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Kaisheng Ma, Xiaoxin Cui, Kai Liao, Nan Liao, Di Wu, Dunshan Yu |
Key characterization factors of accurate power modeling for FinFET circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 58(2), pp. 1-13, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Xianmin Chen, Niraj K. Jha |
gem5-PVT: A Framework for FinFET System Simulation under PVT Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(3), pp. 28:1-28:19, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin |
FinFET-Based Low-Swing Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(2), pp. 13:1-13:20, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Vikas Mahor, Manisha Pattanaik |
Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(2), pp. 225-235, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma 0001 |
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(1), pp. 49-62, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001 |
Variability Influence on FinFET-Based On-Chip Memory Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(2), pp. 250-255, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | K. P. Pradhan, Sushanta Kumar Mohapatra, Prasanna Kumar Sahu |
Design Equivalent Scaling on Double Gate FinFET Towards Analog and RF Figures of Merits: A Technology Computer Aided Design Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(3), pp. 316-322, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Pooja Joshi, Saurabh Khandelwal, Shyam Akashe |
Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(3), pp. 298-307, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis |
Impact of PVT variability on 20 nm FinFET standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(9-10), pp. 1379-1383, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma 0001 |
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(8), pp. 1131-1143, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Usman Khalid, Antonio Mastrandrea, Mauro Olivieri |
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(12), pp. 2614-2626, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Ko-Chun Lee, Ming-Long Fan, Pin Su |
Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(2), pp. 332-336, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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