Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya, Prasanna Venkatesh Kannan	Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design.	IWSOC	2003	DBLP DOI BibTeX RDF
10	Aneesh Koorapaty, Lawrence T. Pileggi	Modular, Fabric-Specific Synthesis for Programmable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
10	Frank Wolz, Reiner Kolla	A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
10	Eric Roesler, Brent E. Nelson	Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture.	FPL	2002	DBLP DOI BibTeX RDF
10	Jan Vorácek, Nina Kontro-Vesivalo	International education in information technology.	ITiCSE	2002	DBLP DOI BibTeX RDF
10	Jason Cong, Joey Y. Lin, Wangning Long	A new enhanced SPFD rewiring algorithm.	ICCAD	2002	DBLP DOI BibTeX RDF
10	Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky	Self-checking sequential circuits with self-healing ability.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF
10	Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang	Unified functional decomposition via encoding for FPGA technology mapping.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
10	Abdel Ejnioui, N. Ranganathan	A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
10	Lech Józwiak, Artur Chojnacki	Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures.	DSD	2001	DBLP DOI BibTeX RDF
10	Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh	Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Andrzej Krasniewski	Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing.	IOLTW	2001	DBLP DOI BibTeX RDF
10	Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya	SPFD: A new method to express functional flexibility.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Fabio Ganovelli, Paolo Cignoni, Claudio Montani, Roberto Scopigno	Enabling Cuts on Multiresolution Representation.	Computer Graphics International	2000	DBLP DOI BibTeX RDF	Level of Details, Multiresolution
10	Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa	The Fastest Multiplier on FPGAs with Redundant Binary Representation.	FPL	2000	DBLP DOI BibTeX RDF
10	Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier	Area-Optimized Technology Mapping for Hybrid FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
10	Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi	Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
10	Artur Chojnacki, Lech Józwiak	Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures.	ISMVL	2000	DBLP DOI BibTeX RDF
10	Andrzej Krasniewski	Self-Testing of FPGA Delay Faults in the System Environment.	IOLTW	2000	DBLP DOI BibTeX RDF	FPGA, BIST, random testing, delay faults
10	Abdel Ejnioui, N. Ranganathan	Design Partitioning on Single-Chip Emulation Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF	FPGA partitioning, integer programming, FPGA architecture, schedule optimization
10	Jason Cong, Hui Huang 0001	Depth optimal incremental mapping for field programmable gate arrays.	DAC	2000	DBLP DOI BibTeX RDF
10	Alireza Kaviani, Stephen Dean Brown	The Hybrid Field-Programmable Architecture.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
10	Cheol-Hee Lee, Eui-Yoon Chung, Chae-Soo Lee, Eung-Joo Lee, Yeong-Ho Ha	Tone reproduction technique using neural network in inkjet printers.	KES	1999	DBLP DOI BibTeX RDF
10	Ilya Levin, Vladimir Sinelnikov	Self-Checking of FPGA-Based Control Units.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
10	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
10	Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda	New FPGA Architecture for Bit-Serial Pipeline Datapath.	FCCM	1998	DBLP DOI BibTeX RDF
10	Matthew Moe, Herman Schmit, Seth Copen Goldstein	Characterization and Parameterization of a Pipeline Reconfigurable FPGA.	FCCM	1998	DBLP DOI BibTeX RDF
10	Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef	Stochastic Evolution Algorithm For Technology Mapping.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Stochastic Evolution, FPGA, Logic Synthesis, Technology mapping, Boolean Network
10	Amit Sinha, Mahesh Mehendale	mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic.	VLSI Design	1998	DBLP DOI BibTeX RDF	FIR Filters, Distributed Arithmetic, Area Estimation
10	Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang	Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.	DAC	1998	DBLP DOI BibTeX RDF
10	Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang	A Re-engineering Approach to Low Power FPGA Design Using SPFD.	DAC	1998	DBLP DOI BibTeX RDF
10	Madhukar R. Korupolu, K. K. Lee, D. F. Wong 0001	Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs.	DAC	1998	DBLP DOI BibTeX RDF
10	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
10	Ronald Jones, Imants D. Svalbe	Morphological Filtering as Template Matching.	IEEE Trans. Pattern Anal. Mach. Intell.	1994	DBLP DOI BibTeX RDF	binary morphology, pattern recognition, image processing, mathematical morphology, pipeline processing, pipeline processing, template matching, filtering and prediction theory, table lookup, lookup table, morphological filtering
10	Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki	A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.	ICCAD	1994	DBLP DOI BibTeX RDF