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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 465 occurrences of 241 keywords
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Results
Found 842 publication records. Showing 835 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya, Prasanna Venkatesh Kannan |
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 44-47, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Aneesh Koorapaty, Lawrence T. Pileggi |
Modular, Fabric-Specific Synthesis for Programmable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 132-141, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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10 | Frank Wolz, Reiner Kolla |
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 997-1006, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Eric Roesler, Brent E. Nelson |
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 637-646, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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10 | Jan Vorácek, Nina Kontro-Vesivalo |
International education in information technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 7th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2002, Aarhus, Denmark, June 24-28, 2002, pp. 245, 2002, ACM, 1-58113-499-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Jason Cong, Joey Y. Lin, Wangning Long |
A new enhanced SPFD rewiring algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 672-678, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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10 | Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky |
Self-checking sequential circuits with self-healing ability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 71-76, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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10 | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang |
Unified functional decomposition via encoding for FPGA technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 251-260, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Abdel Ejnioui, N. Ranganathan |
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 407-410, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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10 | Lech Józwiak, Artur Chojnacki |
Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 30-37, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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10 | Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh |
Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 519-522, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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10 | Andrzej Krasniewski |
Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 37-, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya |
SPFD: A new method to express functional flexibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8), pp. 840-849, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Fabio Ganovelli, Paolo Cignoni, Claudio Montani, Roberto Scopigno |
Enabling Cuts on Multiresolution Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Graphics International ![In: Computer Graphics International Conference, CGI 2000, Geneva, Switzerland, June 19-24, 2000, pp. 183-191, 2000, IEEE Computer Society, 0-7695-0643-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Level of Details, Multiresolution |
10 | Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa |
The Fastest Multiplier on FPGAs with Redundant Binary Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 515-524, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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10 | Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier |
Area-Optimized Technology Mapping for Hybrid FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 181-190, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi |
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 951-958, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Artur Chojnacki, Lech Józwiak |
Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 83-90, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Andrzej Krasniewski |
Self-Testing of FPGA Delay Faults in the System Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 40-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, BIST, random testing, delay faults |
10 | Abdel Ejnioui, N. Ranganathan |
Design Partitioning on Single-Chip Emulation Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 234-239, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA partitioning, integer programming, FPGA architecture, schedule optimization |
10 | Jason Cong, Hui Huang 0001 |
Depth optimal incremental mapping for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 290-293, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Alireza Kaviani, Stephen Dean Brown |
The Hybrid Field-Programmable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(2), pp. 74-83, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Cheol-Hee Lee, Eui-Yoon Chung, Chae-Soo Lee, Eung-Joo Lee, Yeong-Ho Ha |
Tone reproduction technique using neural network in inkjet printers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Third International Conference on Knowledge-Based Intelligent Information Engineering Systems, KES 1999, Adelaide, South Australia, 31 August - 1 September 1999, Proceedings, pp. 103-106, 1999, IEEE, 0-7803-5578-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Ilya Levin, Vladimir Sinelnikov |
Self-Checking of FPGA-Based Control Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 292-295, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Peichen Pan, C. L. Liu 0001 |
Optimal clock period FPGA technology mapping for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(3), pp. 437-462, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis |
10 | Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda |
New FPGA Architecture for Bit-Serial Pipeline Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 58-67, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Matthew Moe, Herman Schmit, Seth Copen Goldstein |
Characterization and Parameterization of a Pipeline Reconfigurable FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 294-295, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef |
Stochastic Evolution Algorithm For Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 380-385, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Stochastic Evolution, FPGA, Logic Synthesis, Technology mapping, Boolean Network |
10 | Amit Sinha, Mahesh Mehendale |
mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 104-109, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
FIR Filters, Distributed Arithmetic, Area Estimation |
10 | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang |
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 712-717, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang |
A Re-engineering Approach to Low Power FPGA Design Using SPFD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 722-725, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Madhukar R. Korupolu, K. K. Lee, D. F. Wong 0001 |
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 708-711, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Stanley Habib, Quan Xu |
Technology mapping algorithms for sequential circuits using look-up table based FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 164-167, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table |
10 | Ronald Jones, Imants D. Svalbe |
Morphological Filtering as Template Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 16(4), pp. 438-443, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
binary morphology, pattern recognition, image processing, mathematical morphology, pipeline processing, pipeline processing, template matching, filtering and prediction theory, table lookup, lookup table, morphological filtering |
10 | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 156-163, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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