Search results for "MPSoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Wei Hu 0001, Tianzhou Chen, Qingsong Shi, Mingteng Cao, Gang Wang	eNSTM: a Nested Software Transactional Memory Framework for MPSoC System.	ESA	2009	DBLP BibTeX RDF
15	Bisrat Tafesse, Venkatesan Muthukumar	Framework for Simulation of Fault Tolerant Heterogeneous MPSOC.	ESA	2009	DBLP BibTeX RDF
15	Sohaib Majzoub, Resve A. Saleh, Rabab K. Ward	PVT variation impact on voltage island formation in MPSoC design.	ISQED	2009	DBLP DOI BibTeX RDF
15	Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne	MPSoC Design Using Application-Specific Architecturally Visible Communication.	HiPEAC	2009	DBLP DOI BibTeX RDF
15	Chun Shing Cheung	MPSoC Simulation and Implementation of KPN Applications.		2009	RDF
15	Sami Boukhechem, El-Bay Bourennane	SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication.	Int. J. Reconfigurable Comput.	2008	DBLP DOI BibTeX RDF
15	Vincent Nollet, Prabhat Avasare, Hendrik Eeckhaut, Diederik Verkest, Henk Corporaal	Run-Time Management of a MPSoC Containing FPGA Fabric Tiles.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski	System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design.	EURASIP J. Embed. Syst.	2008	DBLP DOI BibTeX RDF
15	Katalin Popovici, Xavier Guerin, Frédéric Rousseau 0001, Pier Stanislao Paolucci, Ahmed Amine Jerraya	Platform-based software design flow for heterogeneous MPSoC.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	multimedia, programming environment, software design, SystemC, Simulink, transaction level modeling, Multiprocessor system-on chip
15	Akash Kumar 0001, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha	Analyzing composability of applications on MPSoC platforms.	J. Syst. Archit.	2008	DBLP DOI BibTeX RDF
15	Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi	MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.	DDECS	2008	DBLP DOI BibTeX RDF
15	Alexandre Chureau, Frédéric Pétrot	An intermediate format for automatic generation of MPSoC virtual prototypes.	ICSAMOS	2008	DBLP DOI BibTeX RDF
15	Philip K. F. Hölzenspies, Johann L. Hurink, Jan Kuper, Gerard J. M. Smit	Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC).	DATE	2008	DBLP DOI BibTeX RDF
15	Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle	System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.	DATE	2008	DBLP DOI BibTeX RDF
15	Rolf Ernst, Marek Jersak, Hans Sarnowski, Marco Bekooij, Samarjit Chakraborty	Formal Methods in System and MpSoC Performance Analysis and Optimisation.	DATE	2008	DBLP DOI BibTeX RDF
15	Eduardo Wenzel Brião, Daniel Barcelos, Flávio Rech Wagner	Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications.	DATE	2008	DBLP DOI BibTeX RDF
15	Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto	ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration.	ASP-DAC	2008	DBLP DOI BibTeX RDF
15	Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant, Kenny C. Gross	Temperature-aware MPSoC scheduling for reducing hot spots and gradients.	ASP-DAC	2008	DBLP DOI BibTeX RDF
15	Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi	System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis.	SASP	2008	DBLP DOI BibTeX RDF
15	Kai Sun, Hongxing Wei, Tianmiao Wang, Meng Wang 0005, Zili Shao, Hui Liu 0006	MPSOC Architectural Design and Synthesis for Real-Time Biomedical Signal Processing in Gamma Cameras.	BIODEVICES (2)	2008	DBLP BibTeX RDF
15	Slim Ben Othman, Ahmed Karim Ben Salem, Slim Ben Saoud	MPSoC design of RT control applications based on FPGA SoftCore processors.	ICECS	2008	DBLP DOI BibTeX RDF
15	Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman	MC-Sim: an efficient simulation tool for MPSoC designs.	ICCAD	2008	DBLP DOI BibTeX RDF
15	Maissa Elleuch, Yassine Aydi, Mohamed Abid	Formal Specification of Delta MINs for MPSOC in the ACL2 Logic.	FDL	2008	DBLP DOI BibTeX RDF
15	Alexander Viehl, Björn Sander, Oliver Bringmann 0001, Wolfgang Rosenstiel	Analysis of Non-functional Properties of MPSoC Designs.	FDL (Selected Papers)	2008	DBLP DOI BibTeX RDF
15	Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya	Integrating Abstract NoC Models within MPSoC Design.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
15	Hao Shen, Patrice Gerin, Frédéric Pétrot	Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
15	Sami Boukhechem, El-Bay Bourennane	TLMCO-simulation for an open source MPSOC platform under STARSoC environment.	SoC	2008	DBLP DOI BibTeX RDF
15	Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Ricardo Reis 0001, Xavier Guerin, Ahmed Amine Jerraya	Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.	Des. Autom. Embed. Syst.	2007	DBLP DOI BibTeX RDF
15	Jinyong Jung, Sungjoo Yoo, Kiyoung Choi	Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction.	Des. Autom. Embed. Syst.	2007	DBLP DOI BibTeX RDF
15	Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy	A hardware/software framework for supporting transactional memory in a MPSoC environment.	SIGARCH Comput. Archit. News	2007	DBLP DOI BibTeX RDF
15	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Philip K. F. Hölzenspies, Jan Kuper, Gerard J. M. Smit, Johann L. Hurink	Demonstration of Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC).	Quantitative Aspects of Embedded Systems	2007	DBLP BibTeX RDF
15	Sujan Pandey, Christian Genz, Rolf Drechsler	Co-synthesis of custom on-chip bus and memory for MPSoC architectures.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
15	Christian Sauer 0001, Matthias Gries, Sebastian Dirk	Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform.	DATE	2007	DBLP DOI BibTeX RDF
15	Lucky L. Chi Yu Lo, Samar Abdi	Automatic TLM generation for C-Based MPSoC design.	HLDVT	2007	DBLP DOI BibTeX RDF
15	Brett H. Meyer, Donald E. Thomas	Rethinking Automated Synthesis of MPSoC Architectures.	IPDPS	2007	DBLP DOI BibTeX RDF
15	Brett H. Meyer, Donald E. Thomas	Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	bus architecture synthesis, embedded multiprocessor systems-on-chip, partitioning, sharing, memory allocation, data mapping
15	Qiwei Zhang, André B. J. Kokkeler, Gerard J. M. Smit	Cognitive Radio Design on an MPSoC Reconfigurable Platform.	CrownCom	2007	DBLP DOI BibTeX RDF
15	Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser	Multilevel MPSOC simulation using an MDE approach.	SoCC	2007	DBLP DOI BibTeX RDF
15	Philip K. F. Hölzenspies, Gerard J. M. Smit, Jan Kuper	Mapping streaming applications on a reconfigurable MPSoC platform at run-time.	SoC	2007	DBLP DOI BibTeX RDF
15	Zhiming Tan, Shibao Zheng, Jianling Hu, Yingqi Chen, Peilin Liu	Design and implementation of the software system on MPSoC: An HDTV decoder case study.	IEEE Trans. Consumer Electron.	2006	DBLP DOI BibTeX RDF
15	Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici	Analysis and Optimization of MPSoC Reliability.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
15	Vincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal	Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment.	ERSA	2006	DBLP BibTeX RDF
15	Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini	An integrated open framework for heterogeneous MPSoC design space exploration.	DATE	2006	DBLP DOI BibTeX RDF
15		4G applications, architectures, design methodology and tools for MPSoC.	DATE	2006	DBLP DOI BibTeX RDF
15	Víctor Reyes, Wido Kruijtzer, Tomás Bautista, Ghiath Alkadi, Antonio Núñez	A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study.	DATE	2006	DBLP DOI BibTeX RDF
15	Akash Kumar 0001, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha	Global Analysis of Resource Arbitration for MPSoC.	DSD	2006	DBLP DOI BibTeX RDF
15	Bilel Belhadj Mohamed, Chiheb Rebai, Adel Ghazel	Intra- and Inter-Processors Memory Size Estimation for Multithreaded MPSoC Modeled in Simulink.	ICECS	2006	DBLP DOI BibTeX RDF
15	Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson	MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	hardware space exploration, multiprocessor system-on-chip, real-time analysis, electrocardiogram algorithms
15	Sujan Pandey, Manfred Glesner	Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Erno Salminen, Tero Kangas, Timo Hämäläinen 0001	The Impact of Communication on the Scalability of the Data-parallel Video Encoder on MPSoC.	SoC	2006	DBLP DOI BibTeX RDF
15	Rabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser	Multilevel MPSoC Performance Evaluation Using MDE Approach.	SoC	2006	DBLP DOI BibTeX RDF
15	Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena	Model Driven Engineering for Regular MPSoC Co-design.	ReCoSoC	2005	DBLP BibTeX RDF
15	Balal Ahmad, Tughrul Arslan	Dynamically reconfigurable NoC for reconfigurable MPSoC.	CICC	2005	DBLP DOI BibTeX RDF
15	Ali Erdem Özcan, Oussama Layaida, Jean-Bernard Stefani	A Component-based Approach for MPSoC SW Design: Experience with OS Customization for H.264 Decoding.	ESTIMedia	2005	DBLP DOI BibTeX RDF
15	Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini	Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms.	ICCD	2005	DBLP DOI BibTeX RDF
15	Özcan Özturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun	On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression.	SoCC	2005	DBLP DOI BibTeX RDF
15	Wayne H. Wolf	Embedded computer architectures in the MPSoC age.	WCAE@ISCA	2005	DBLP DOI BibTeX RDF
15	Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi	Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design.	DAC	2005	DBLP DOI BibTeX RDF	multimedia, workload, system-level design
15	Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon	Analyzing On-Chip Communication in a MPSoC Environment.	DATE	2004	DBLP DOI BibTeX RDF
15	Arnaud Grasset, Frédéric Rousseau 0001, Ahmed Amine Jerraya	Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
15	Alexander Maxiaguine, Samarjit Chakraborty, Wei Tsang Ooi	Identifying "representative" workloads in designing MpSoC platforms for media processing.	ESTIMedia	2004	DBLP DOI BibTeX RDF
11	Siddharth Garg, Diana Marculescu, Radu Marculescu	Custom feedback control: enabling truly scalable on-chip power management for MPSoCs.	ISLPED	2010	DBLP DOI BibTeX RDF	distributed control, dynamic voltage/frequency scaling
11	Jason Cong, Chunyue Liu, Glenn Reinman	ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	application-specific Network-on-Chip, deadlock-free routing
11	Khaled Z. Ibrahim, Smaïl Niar	Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
11	Xinyu Li, Omar Hammami	Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, multiprocessor, network on chip
11	Marcio F. da S. Oliveira, Ronaldo Rodrigues Ferreira, Francisco Assis Moreira do Nascimento, Franz J. Rammig, Flávio Rech Wagner	Exploiting the model-driven engineering approach to improve design space exploration of embedded systems.	SBCCI	2009	DBLP DOI BibTeX RDF	embedded systems, model-driven engineering, design space exploration
11	Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001	A path-load based adaptive routing algorithm for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	quality of service, networks on chip, dynamic routing, traffic monitoring
11	Jason Agron, David Andrews 0001	Building heterogeneous reconfigurable systems with a hardware microkernel.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	FPGAs, operating systems, heterogeneous architectures
11	Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	TotalProf: a fast and accurate retargetable source code profiler.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	source code profiling, architecture description language, performance estimation, instruction set simulation
11	Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001	A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	QoS, networks on chip, dynamic routing, traffic monitoring
11	Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin	The Need for Reconfigurable Routers in Networks-on-Chip.	ARC	2009	DBLP DOI BibTeX RDF	heterogeneous NoC, reconfigurable router, buffer, FIFO
11	Yongji Jiang, Garrett S. Rose	A dual-MOSFET equivalent resistor thermal sensor.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	integrated circuits, dynamic thermal management, vlsi, temperature sensors
11	Tom van den Broek, Julien Schmaltz	Towards a formally verified network-on-chip.	FMCAD	2009	DBLP DOI BibTeX RDF
11	Ayse K. Coskun, Tajana Simunic Rosing, Keith Whisnant, Kenny C. Gross	Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Guilin Chen, Mahmut T. Kandemir	Compiler-Directed Code Restructuring for Improving Performance of MPSoCs.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
11	Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev	A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hardware space exploration, embedded system design, Multiprocessor system-on-chip, real time analysis, electrocardiogram algorithms
11	Akash Kumar 0001, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal	Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	multi-application, multiple use-cases, synchronous data-flow graphs, FPGA, multiprocessor systems, multimedia systems, design exploration
11	Chris R. Jesshope	Introduction to Programming Multicores.	SAMOS	2008	DBLP DOI BibTeX RDF
11	Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu	Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs.	DATE	2008	DBLP DOI BibTeX RDF
11	Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli	Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures.	DATE	2008	DBLP DOI BibTeX RDF
11	Grégory Gailliard, Hugues Balp, Michel Sarlotte, François Verdier	Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components.	DATE	2008	DBLP DOI BibTeX RDF
11	Lisane B. de Brisolara, Marcio F. da S. Oliveira, Ricardo Miotto Redin, Luís C. Lamb, Luigi Carro, Flávio Rech Wagner	Using UML as Front-end for Heterogeneous Software Code Generation Strategies.	DATE	2008	DBLP DOI BibTeX RDF
11	Sudeep Pasricha, Nikil D. Dutt	ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park	A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Gunar Schirner, Andreas Gerstlauer, Rainer Dömer	Automatic generation of hardware dependent software for MPSoCs from abstract system specifications.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Jason Wu, John Williams 0004, Neil W. Bergmann	An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC.	FPL	2008	DBLP DOI BibTeX RDF
11	Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khonsari, Mohammad Hossien Yaghmaee	Proportionally-fair best effort flow control in network-on-chip architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
11	Konstantinos Aisopos, Chien-Chun Chou, Li-Shiuan Peh	Extending open core protocol to support system-level cache coherence.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	coherence extensions, ocp, open core protocol, specification, mpsocs
11	Haris Javaid, Sri Parameswaran	Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	design space exploration, integer linear programming, MPSoCs
11	Kai Huang 0001, Iuliana Bacivarov, Fabian Hugelshofer, Lothar Thiele	Scalably distributed SystemC simulation for embedded applications.	SIES	2008	DBLP DOI BibTeX RDF
11	Elias Teodoro Silva Jr., Daniel Barcelos, Flávio Rech Wagner, Carlos Eduardo Pereira	A virtual platform for multiprocessor real-time embedded systems.	JTRES	2008	DBLP DOI BibTeX RDF	real-time systems, energy efficiency, network on chip, embedded applications
11	Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi	A Performance Model of Communication in the Quarc NoC.	ICPADS	2008	DBLP DOI BibTeX RDF
11	Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar	Multi-granularity sampling for simulating concurrent heterogeneous applications.	CASES	2008	DBLP DOI BibTeX RDF	simulation sampling, multiprocessor system-on-chip, simulation acceleration
11	Wei Han 0001, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet Teyfik Erdogan	MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.	SoCC	2008	DBLP DOI BibTeX RDF
11	Georges G. E. Gielen, Donatella Sciuto	Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Youcef Bouchebaba, Bruno Girodias, Fabien Coelho, Gabriela Nicolescu, El Mostapha Aboulhamid	Buffer and Register Allocation for Memory Space Optimization.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	program transformation, memory hierarchy, data locality, memory optimization
11	Hansu Cho, Samar Abdi, Daniel Gajski	Interface synthesis for heterogeneous multi-core systems from transaction level models.	LCTES	2007	DBLP DOI BibTeX RDF	HW-SW co-design, universal bridge, channel, transaction level model, communication synthesis, interface synthesis
11	Donghyun Kim, Kwanho Kim, Joo-Young Kim 0001, Seungjin Lee 0001, Hoi-Jun Yoo	Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.	NOCS	2007	DBLP DOI BibTeX RDF
11	Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor	Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.	SAMOS	2007	DBLP DOI BibTeX RDF