Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Bernard Girau, César Torres-Huitzil |
Fast Implementation of a Bio-inspired Model for Decentralized Gathering. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
decentralized gathering, FPGA, distributed computing |
1 | Daniele Fronte, Annie Pérez, Eric Payrat |
Celator: A Multi-algorithm Cryptographic Co-processor. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
key cryptography, Systolic Processors, Cryptography, Smart cards, AES, Communication system security |
1 | Sven Eisenhardt, Tobias Oppold, Thomas Schweizer, Wolfgang Rosenstiel |
Optimizing Partial Reconfiguration of Multi-context Architectures. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
dynamic reconfiguration, array, partial reconfiguration, coarse-grained, multi-context |
1 | Coral Gonzalez-Concejero, Victoria Rodellar, Agustín Álvarez Marquina, Elvira Martínez de Icaya, Pedro Gómez Vilda |
An FFT/IFFT Design versus Altera and Xilinx Cores. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Song Sun, Michael Steffen, Joseph Zambreno |
A Reconfigurable Platform for Frequent Pattern Mining. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval |
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
AES-CCM, Wireless Networks, FPGA Implementation |
1 | Sheng Cheng, Chien-Hsun Tseng, Marina Cole |
A Novel FPGA Implementation of a Wideband Sonar System for Target Motion Estimation. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Wideband Sonar System, CWT, FPGA, DWT |
1 | Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara 0001, Naofumi Homma, Takafumi Aoki |
Enhanced Correlation Power Analysis Using Key Screening Technique. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA, side-channel attack, power analysis, CPA |
1 | Zobeida Jezabel Guzman-Zavaleta, Claudia Feregrino Uribe, René Cumplido |
A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Radiological Medical Images, FPGAs, Hardware Implementation, Reversible Data Hiding |
1 | Karel Bruneel, Dirk Stroobandt |
Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA, CAD, dynamic reconfiguration, technology mapping |
1 | Anabel Morales-Cortes, Ramón Parra-Michel, Luis F. Gonzalez-Perez, Gabriela Cervantes T. |
Finite Precision Analysis of the 3GPP Standard Turbo Decoder for Fixed-Point Implementation in FPGA Devices. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Anders Kjær-Nielsen, Lars Baunegaard With Jensen, Anders Stengaard Sørensen, Norbert Krüger |
A Real-Time Embedded System for Stereo Vision Preprocessing Using an FPGA. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Stereo Vision Preprocessing, 1394a, FPGA, Real-time, Embedded, FireWire |
1 | Manuel Saldaña, Emanuel Ramalho, Paul Chow |
A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Simulation, FPGA, Parallel Programming, MPI, Message-Passing, Reconfigurable, High-Performance |
1 | Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido |
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
MCLT, Watermarking Systems, FPGA |
1 | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres |
Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Abdulrahman Hanoun, Friedrich Mayer-Lindenberg, Bassel Soudan |
Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
2D pipeline, Baugh-Wooley, Reconfigurable, Multiplier, distributed arithmetic, Systolic |
1 | Rohit Saraswat, Brandon Eames |
Finite Domain Constraints Based Delay Aware Placement Tool for FPOAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPOA, Placement, Constraint Satisfaction, Coarse grained reconfigurable architecture, Finite Domain Constraints |
1 | Philipp Mahr, Christian Lorchner, Harold Ishebabi, Christophe Bobda |
SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA, communication, networks, MPI, MPSoC |
1 | Luiza M. N. Coutinho, José Leandro D. Mendes, Carlos A. P. S. Martins |
Dynamically Reconfigurable Split Cache Architecture. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Computer Architecture, Reconfigurable Computing, Cache memories |
1 | Tom Degryse, Karel Bruneel, Harald Devos, Dirk Stroobandt |
Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Dynamic hardware generation, FPGAs, Matrix multiplications, Loop transformations |
1 | Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello |
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
multimedia, reconfigurable, SIMD, datapath |
1 | Juan A. Rico-Gallego, Jesús M. Álvarez Llorente, Francisco J. Perogil-Duque, Pedro P. Antunez-Gomez, Juan Carlos Díaz Martín |
A Pthreads-Based MPI-1 Implementation for MMU-Less Machines. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA, MPI, Pthreads |
1 | César Torres-Huitzil, Bernard Girau, Amine M. Boumaza, Bruno Scherrer |
Embedded Harmonic Control for Trajectory Planning in Large Environments. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
harmonic control, FPGA, embedded systems, trajectory planning |
1 | Carlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels |
Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Simon Banks, Philip Beadling, Andras Ferencz |
FPGA Implementation of Pseudo Random Number Generators for Monte Carlo Methods in Quantitative Finance. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Monte Carlo Methods in Finance, FPGA, Pseudo Random Number, Mersenne Twister |
1 | Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez |
Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Discrete Signal Transforms, Custom Computing Architectures, FPGA, Resource Estimation |
1 | Humberto Calderon, Jesús Ortiz 0001, Jean-Guy Fontaine |
Disparity Map Hardware Accelerator. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA, computer vision, computer arithmetic, Hardware accelerators, disparity map |
1 | Manuel Hernandez Calviño, Sergio Ruben Geninatti, José Ignacio Benavides Benítez |
Developing an MMX Extension for the MicroBlaze Soft Processor. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
MicroBlaze, FPGA, MMX, FSL |
1 | Xiaofang Wang, Swetha Thota |
Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, multiprocessor, network-on-chip |
1 | Griselda Saldaña, Miguel Arias-Estrada |
Real Time FPGA-based Architecture for Video Applications. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ulises S. Mendoza-Camarena, René de Jesús Romero-Troncoso |
VHDL Core for the Computation of the One-Dimensional Discrete Cosine Transform. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Miguel Morales-Sandoval, Claudia Feregrino Uribe |
GF(2m) Arithmetic Modules for Elliptic Curve Cryptography. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jorge Luiz e Silva, Eduardo Marques |
Executing Algorithms for Dynamic Dataflow Reconfigurable Hardware -The Operators Protocol. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Javier Castillo, Pablo Huerta, César Pedraza, José Ignacio Martínez |
A Self-Reconfigurable Multimedia Player on FPGA. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón, Rudi H. van Els |
Implementation, Simulation and Validation of Dispatching Algorithms for Elevator Systems. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ahmed Elhossini, Shawki Areibi, Robert D. Dony |
An FPGA Implementation of the LMS Adaptive Filter for Audio Processing. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Omar Piña-Ramirez, Raquel Valdés-Cristerna, Oscar Yáñez-Suárez |
An FPGA Implementation of Linear Kernel Support Vector Machines. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Steven Bishop, Suresh Rai, Bahadir K. Gunturk, Jerry L. Trahan, Ramachandran Vaidyanathan |
Reconfigurable Implementation of Wavelet Integer Lifting Transforms for Image Compression. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Thorsten von Sydow, Matthias Korb, Bernd Neumann, Holger Blume, Tobias G. Noll |
Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Marcos R. de Alba-Rosano, Andrés David García García |
Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Timothy Lantz, Eric Peskin |
A QCA Implementation of a Configurable Logic Block for an FPGA. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Carlos E. Gutiérrez Salmeron, Andrés David García García, Reynaldo Félix Acuña |
Bio - Inspired & Traditional Approaches to Obtain Fault Tolerance. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Yogindra Abhyankar, C. Sajish, Yogesh Agarwal, C. R. Subrahmanya, Peeyush Prasad |
High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing Platform. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Rashad S. Oreifej, Carthik A. Sharma, Ronald F. DeMara |
Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | José Martínez, Leopoldo Altamirano Robles |
FPGA-based Pipeline Architecture to Transform Cartesian Images into Foveal Images by Using a new Foveation Approach. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Andres Cicuttin, Maria Liz Crespo, Alexander Shapiro, Nizar Abdallah |
A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA Technology. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Elvira Martínez de Icaya, Victoria Rodellar, Coral Gonzalez-Concejero, Virginia Peinado, Vicente Angel García |
Design Space Exploration for an Adaptive Noise Cancellation Algorithm. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst |
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Pedro Gómez 0001, Francisco Díaz Pérez, Bogdan Belean, Raul Malutan, Benjamin Stetter, Rafael Martínez 0001, Victoria Rodellar |
Robust cDNA microarray image processing on a hand-held device. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Maurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy |
A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Marcos Vinícius da Silva, Ricardo S. Ferreira 0001, Alisson Garcia, João M. P. Cardoso |
Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga |
Realization of the sound space environment for the radiation-tolerant space craft. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, Paul Chow |
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Santos López-Estrada, René Cumplido |
Decision Tree Based FPGA-Architecture for Texture Sea State Classification. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Julio A. de Oliveira Filho, Thomas Schweizer, Tobias Oppold, Tommy Kuhn, Wolfgang Rosenstiel |
Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Marcelo Götz, Florian Dittmann 0001 |
Reconfigurable Microkernel-based RTOS: Mechanisms and Methods for Run-Time Reconfiguration. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Nilton B. Armstrong, Heitor S. Lopes, Carlos Raimundo Erig Lima |
Preliminary Steps Towards Protein Folding Prediction Using Reconfigurable Computing. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Florian Dittmann 0001, Achim Rettberg, Raphael Weber |
Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl |
Datapath and ISA Customization for Soft VLIW Processors. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Guilherme Luiz Moritz, Cristiano Jory, Heitor S. Lopes, Carlos Raimundo Erig Lima |
Implementation of a Parallel Algorithm for Protein Pairwise Alignment Using Reconfigurable Computing. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Heng Tan, Ronald F. DeMara |
A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | René Cumplido-Parra, César Torres-Huitzil, Andrés D. García (eds.) |
2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006 |
ReConFig |
2006 |
DBLP BibTeX RDF |
|
1 | AbdelHalim Samahi, El-Bay Bourennane, Sami Boukhechem |
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ameet Chavan, Gaurav Dukle, Ben Graniello, Eric W. MacDonald |
Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jose Alberto Vite-Frias, Arturo Garcia-Perez |
8-bit CISC Microprocessor Core for Teaching Applications in the Digital Systems Laboratory. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jorge Alberto Surís, Peter M. Athanas |
Exploring Non-Traditional Hardware-Software Interaction. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Gerardo Eli Martínez-Torres, J. M. Luna-Rivera, Raul E. Balderas-Navarro |
FPGA-Based Educational Platform for Wireless Transmission Using System Generator. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Julio C. G. Pimentel |
Implementation of Simulation Algorithms in FPGA for Real Time Simulation of Electrical Networks with Power Electronics Devices. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Julio C. Sosa, Rocío Gómez-Fabela, Jose Antonio Boluda, Fernando Pardo |
Change-driven Image Architecture on FPGA with adaptive threshold for Optical-Flow Computation. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer |
A Reconfigurable Simulation Framework for Financial Computation. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jorge Peña 0001, Mauricio Vanegas, Andrés Valencia |
Digital Hardware Architectures of Kohonen's Self Organizing Feature Maps with Exponential Neighboring Function. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Oliver Pell, Wayne Luk |
Quartz: a framework for correct and efficient reconfigurable design. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Joaquín García 0003, René Cumplido-Parra |
On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo |
FPGA implementation of a synchronous and self-timed neuroprocessor. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Patrick Rocke, John Maher, Fearghal Morgan |
Platform for intrinsic evolution of analogue neural networks. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | José Francisco Martínez Trinidad, René Cumplido-Parra, Claudia Feregrino Uribe |
An FPGA-based parallel sorting architecture for the Burrows Wheeler transform. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Mario Alberto Garcia Martinez, Rubén Posada-Gómez, Guillermo Morales-Luna, Francisco Rodríguez-Henríquez |
FPGA implementation of an efficient multiplier over finite fields GF(2m). |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | |
2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005 |
ReConFig |
2005 |
DBLP BibTeX RDF |
|
1 | Vijay Pandya, Shawki Areibi, Medhat Moussa |
A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Kimmo Rauma, Julius Luukko, Torsti Härkönen, Ilkka Pajari, Olli Pyrhönen |
A novel FPGA implementation of a welding control using a new bus architecture. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | André L. S. Braga, Carlos H. Llanos, Mauricio Ayala-Rincón, Ricardo P. Jacobi |
VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Corey J. Milliord, Carthik A. Sharma, Ronald F. DeMara |
Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Fearghal Morgan, Patrick Rocke, Martin O'Halloran |
Applied VHDL training methodology, EDA framework and hardware implementation platform. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Annie Avakian, Iyad Ouaiss |
Optimizing register binding in FPGAs using simulated annealing. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | David B. Thomas, Wayne Luk |
High quality uniform random number generation for massively parallel simulations in FPGA. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Jose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno |
VHDL core for 1024-point radix-4 FFT computation. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Guillermo Marcus, Juan Arturo Nolazco-Flores |
An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Alfonso Ávila 0001, Rolando Santoyo-Rincón, Sergio Omar Martinez-Chapa, Graciano Dieck-Assad |
Hardware/software implementation of a discrete cosine transform algorithm using SystemC. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek |
Design space exploration of coarse-grain reconfigurable DSPs. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Sebastian Lange, Martin Middendorf |
On the design of two-level reconfigurable architectures. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Griselda Saldaña, Miguel Arias-Estrada |
FPGA-based customizable systolic architecture for image processing applications. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Ossi Laakkonen, Hannu Sarén, Kimmo Rauma, Olli Pyrhönen |
FPGA implementation of DSVPWM modulator. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Miguel Angel Sánchez Martínez, Adriano De Luca Pennacchia |
An image comparison circuit design. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Sabel Mercurio Hernández Rodríguez, Francisco Rodríguez-Henríquez |
An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo |
Rapid prototyping of a self-timed ALU with FPGAs. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Javier Castillo, Pablo Huerta, Víctor López, José Ignacio Martínez |
A secure self-reconfiguring architecture based on open-source hardware. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Snaider L. Carrillo, Agenor Z. Polo, Mario P. Esmeral |
Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Alejandro Ordaz-Moreno, René de Jesús Romero-Troncoso, Jose Alberto Vite-Frias |
Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada |
Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling. |
ReConFig |
2005 |
DBLP DOI BibTeX RDF |
|