Search results for "SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
11	Jae-Won Nam, Ju-Hyeok Ahn, Jong-Phil Hong	Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique.	IEEE Access	2022	DBLP DOI BibTeX RDF
11	Jaeseong Lee 0005, Piljoo Choi, Dong Kyue Kim	Lightweight and Low-Latency AES Accelerator Using Shared SRAM.	IEEE Access	2022	DBLP DOI BibTeX RDF
11	Keisuke Kozu, Yuya Tanabe, Masato Kitakami, Kazuteru Namba	Low Power Neural Network by Reducing SRAM Operating Voltage.	IEEE Access	2022	DBLP DOI BibTeX RDF
11	Azam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg	Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements.	IEEE Access	2022	DBLP DOI BibTeX RDF
11	Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni 0004, Peter Debacker, Asen Asenov, Aida Todri-Sanial	Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
11	Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha	A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
11	Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni 0004, Peter Debacker, Asen Asenov, Aida Todri-Sanial	Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
11	O. Mohana Chandrika, M. Siva Kumar	Design and analysis of SRAM cell using reversible logic gates towards smart computing.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
11	Fan Zhang, Chenguang Guo, Shifeng Zhang, Qinqin Zeng, Tri Gia Nguyen	A genetic algorithm-based on-orbit self-repair implementation for SRAM FPGAs.	Expert Syst. J. Knowl. Eng.	2022	DBLP DOI BibTeX RDF
11	Zhen Gao 0005, Jinhua Zhu, Tong Yan Tyan, Anees Ullah, Pedro Reviriego	Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
11	Junchao Chen 0001, Thomas Lange, Marko S. Andjelkovic, Aleksandar Simevski, Lu Li, Milos Krstic	Solar Particle Event and Single Event Upset Prediction from SRAM-Based Monitor and Supervised Machine Learning.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
11	T. Venkata Lakshmi, M. Kamaraju	A Review on SRAM Memory Design Using FinFET Technology.	Int. J. Syst. Dyn. Appl.	2022	DBLP DOI BibTeX RDF
11	Bhawna Rawat, Poornima Mittal	A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Morteza Gholipour	Design of a Highly Stable and Robust 10T SRAM Cell for Low-Power Portable Applications.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Elangovan Mani, Morteza Gholipour, Mehrzad Karamimanesh, Mohd Sahid, Adil Zaidi	A Schmitt-Trigger-Based Low-Voltage 11 T SRAM Cell for Low-Leakage in 7-nm FinFET Technology.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
11	Salimeh Shahrabadi	Challenges and solutions of working under threshold supply-voltage, for CNTFET-based SRAM-bitcell.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
11	Uma Maheshwar Janniekode, Rajendra Prasad Somineni, Osamah Ibrahim Khalaf, Malakeh Muhyiddeen Itani, Jyothi Chinna Babu, Ghaida Muttashar Abdulsahib	A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications.	Symmetry	2022	DBLP DOI BibTeX RDF
11	Soumitra Pal 0002, Wing-Hung Ki, Chi-Ying Tsui	Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Samuel Spetalnick, Arijit Raychowdhury	A Practical Design-Space Analysis of Compute-in-Memory With SRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	He Zhang 0011, Junzhan Liu, Jinyu Bai, Sai Li, Lichuan Luo, Shaoqian Wei, Jianxin Wu, Wang Kang 0001	HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Junjie Mu, Hyunjoon Kim, Bongjin Kim	SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Erfan Abbasian	A Highly Stable Low-Energy 10T SRAM for Near-Threshold Operation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Léopold Van Brandt, Roghayeh Saeidi, David Bol, Denis Flandre	Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Farzaneh Izadinasab, Morteza Gholipour	A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Lu Lu 0013, Taegeun Yoo, Tony Tae-Hyoung Kim	A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro	ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
11	Lu Lu 0013, Tony Tae-Hyoung Kim	A High Reliable SRAM-Based PUF With Enhanced Challenge-Response Space.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
11	Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang 0001	A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
11	Yizhak Shifman, Joseph Shor	Preselection Methods to Achieve Very Low BER in SRAM-Based PUFs - A Tutorial.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
11	Yongqiang Zhang 0006, Chunsong Zhu, Xin Cheng 0001, Guangjun Xie	Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
11	Sunghoon Kim, Wonjae Lee, Sundo Kim, Sungjin Park, Dongsuk Jeon	An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
11	Keonhee Cho, Juhyun Park, Ki-Ryong Kim, Tae Woo Oh, Seong-Ook Jung	SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
11	Sujata Pandey, Saket Kumar, Vipul Bhatnagar, Richa Sharma, D. Baba basha, Preeti Dhiman	A low leakage substrate bias-assisted technique for low voltage dual bit-line SRAM.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
11	Marco Grossi, Meryem Bouras, Martin Omaña 0001, Hassan Berbia	Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
11	V. K. Tomar, Ashish Sachdeva	Design of a soft error hardened SRAM cell with improved access time for embedded systems.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
11	Ashish Sachdeva, V. K. Tomar	Characterization of Stable 12T SRAM with Improved Critical Charge.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
11	M. Elangovan, M. Muthukrishnan	A Low-Power and High-Stability 8T SRAM Cell with Diode-Connected Transistors.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
11	Harekrishna Kumar, V. K. Tomar	Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
11	Zeyu Li, Pengfei Yang 0001, Zhao Huang, Quan Wang 0006	AM&FT: An Aging Mitigation and Fault Tolerance Framework for SRAM-Based FPGA in Space Applications.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
11	N. Vinodhkumar, G. Durga, S. Muthumanickam	Numerical Study on SEU Performance of Strain Engineered 6T-SRAM Cells.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
11	M. Elangovan, M. Muthukrishnan	Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
11	Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Zuo-Wei Yeh, Zhaofang Li, Chih-Cheng Lu, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang	MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
11	Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang 0009, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-Sun Seo, Yu Cao 0001	Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Shilpi Birla, Emad Mojaveri Moslem	Design and investigation of stability- and power-improved 11T SRAM cell for low-power devices.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Morteza Gholipour	A low-leakage single-bitline 9T SRAM cell with read-disturbance removal and high writability for low-power biomedical applications.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
11	Rohit Lorenzo, Roy Paily	Half-selection disturbance free 8T low leakage SRAM cell.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
11	Saleh Abdel-Hafeez, Sanabel Otoom, Muhannad Quwaider	Design of memory Alias Table based on the SRAM 8T-Cell.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
11	Damodhar Rao M., Y. V. Narayana, V. V. K. D. V. Prasad	Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells.	Sustain. Comput. Informatics Syst.	2022	DBLP DOI BibTeX RDF
11	Zhi-Wei Lai, Po-Hua Huang, Kuen-Jong Lee	Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
11	Neha Pannu, Neelam Rup Prakash, Jasbir Kaur	Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
11	Wendong Wang, Adit D. Singh, Ujjwal Guin	A Systematic Bit Selection Method for Robust SRAM PUFs.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
11	Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan	Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
11	Abhay S. Vidhyadharan, Sanjay Vidhyadharan	CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
11	Vipul Bhatnagar, Manoj Kumar Pandey, Sujata Pandey	A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
11	Ancy Joy, Jinsa Kuruvilla	A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
11	Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel	Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution.	ACM J. Emerg. Technol. Comput. Syst.	2022	DBLP DOI BibTeX RDF
11	Govind Prasad, Bipin Chandra Mandi, Maifuz Ali	Energy-efficient radiation hardened SRAM cell for low voltage terrestrial applications.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Shilpi Birla, Morteza Gholipour	Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
11	Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal	Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
11	Yue Zhao, Jinkai Wang, Zhongzhen Tong, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao 0007, Zhiting Lin	An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
11	Epiphany Jebamalar Leavline, Somasekaran Sujitha	Design of FinFET based low power, high speed hybrid decoder for SRAM.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
11	Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang 0001	A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
11	Saeed Seyedfaraji, Baset Mesgari, Semeen Rehman	SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology.	CoRR	2022	DBLP DOI BibTeX RDF
11	Guodong Yin, Mufeng Zhou, Yiming Chen, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li	A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface.	CoRR	2022	DBLP DOI BibTeX RDF
11	Joonhyung Kim, Kyeongho Lee, Jongsun Park 0001	A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing.	CoRR	2022	DBLP DOI BibTeX RDF
11	Saeed Seyedfaraji, Baset Mesgari, Semeen Rehman	AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator.	CoRR	2022	DBLP DOI BibTeX RDF
11	Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou	A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization.	CoRR	2022	DBLP DOI BibTeX RDF
11	Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis	An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology.	CoRR	2022	DBLP DOI BibTeX RDF
11	Jingyao Zhang 0002, Hoda Naghibijouybari, Elaheh Sadredini	Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption.	CoRR	2022	DBLP DOI BibTeX RDF
11	Jingyao Zhang 0002, Elaheh Sadredini	Inhale: Enabling High-Performance and Energy-Efficient In-SRAM Cryptographic Hash for IoT.	CoRR	2022	DBLP DOI BibTeX RDF
11	Shan Shen, Peng Cao 0002, Ming Ling, Longxing Shi	A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model.	CoRR	2022	DBLP BibTeX RDF
11	Shu-Hung Kuo, Tian-Sheuan Chang	PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting.	CoRR	2022	DBLP DOI BibTeX RDF
11	Yiming Chen, Yushen Fu, Mingyen Lee, Sumitha George, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li	FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications.	CoRR	2022	DBLP DOI BibTeX RDF
11	Vishal Sharma 0004, Ju Eon Kim, Hyunjoon Kim, Lu Lu 0013, Tony Tae-Hyoung Kim	A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2022	DBLP DOI BibTeX RDF
11	Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni	Enabling In-Memory Computations in Non-Volatile SRAM Designs.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2022	DBLP DOI BibTeX RDF
11	Injun Choi, Edward Jongyoon Choi, Donghyeon Yi, Yoontae Jung, Hoyong Seong, Hyuntak Jeon, Soon-Jae Kweon, Ik-Joon Chang, Sohmyung Ha, Minkyu Je	An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2022	DBLP DOI BibTeX RDF
11	Michael Amar, Amit Kama, Kang Wang, Yossi Oren	Comment on "SRAM-PUF Based Entities Authentication Scheme for Resource-constrained IoT Devices".	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
11	Tomoki Kaneko, Hirobumi Saito, Akira Hirose	SRAM: A Septum-Type Polarizer Design Method Based on Superposed Even- and Odd-Mode Excitation Analysis.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
11	Dashan Shi, Heng You, Jia Yuan, Yulian Wang, Shushan Qiao	A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
11	Bharathi Raj Muthu, Ewins Pon Pushpa, Vaithiyanathan Dhandapani, Kamala Jayaraman, Hemalatha Vasanthakumar, Won-Chun Oh, Suresh Sagadevan	Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell.	Sensors	2022	DBLP DOI BibTeX RDF
11	Muhammad Bintang Gemintang Sulaiman, Jin-Yu Lin, Jian-Bai Li, Cheng-Ming Shih, Kai-Cheung Juang, Chih-Cheng Lu	SRAM-Based CIM Architecture Design for Event Detection.	Sensors	2022	DBLP DOI BibTeX RDF
11	Jialu Yin, Jia Yuan, Zhi Li, Shushan Qiao	A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
11	Dashan Shi, Jia Yuan, Jialu Yin, Yulian Wang, Shushan Qiao	A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
11	Bo-Xi Lai, Shih-Hsu Huang, Hsu-Yu Kao	A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration.	ICCE-TW	2022	DBLP DOI BibTeX RDF
11	Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi	Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell.	MWSCAS	2022	DBLP DOI BibTeX RDF
11	Roberto Román, Rosario Arjona, Iluminada Baturone	Post-quantum Secure Communication with IoT Devices Using Kyber and SRAM Behavioral and Physical Unclonable Functions (Extended Abstract).	ADIoT	2022	DBLP DOI BibTeX RDF
11	Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Andrés Santana-Andreo, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández 0001	A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies.	IRPS	2022	DBLP DOI BibTeX RDF
11	Shayesteh Masoumian, Georgios N. Selimis, Rui Wang, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil	Reliability Analysis of FinFET-Based SRAM PUFs for 16nm, 14nm, and 7nm Technology Nodes.	DATE	2022	DBLP DOI BibTeX RDF
11	Saeed Seyedfaraji, Baset Mesgari, Semeen Rehman	AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator.	DATE	2022	DBLP DOI BibTeX RDF
11	Adarsh Kosta, Efstathia Soufleri, Indranil Chakraborty, Amogh Agrawal, Aayush Ankit, Kaushik Roy 0001	HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive Xbars.	DATE	2022	DBLP DOI BibTeX RDF
11	Saeed Seyedfaraji, Baset Mesgari, Semeen Rehman	SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology.	DSD	2022	DBLP DOI BibTeX RDF
11	Qian Zou, Ning Zhang, Feng Guo, Qingshan Kong, Zhiqiang Lv	Multi-region SRAM-Based TCAM for Longest Prefix.	SciSec	2022	DBLP DOI BibTeX RDF
11	Shengyu Duan, Gaole Sai	Protecting SRAM PUF from BTI Aging-based Cloning Attack.	SBCCI	2022	DBLP DOI BibTeX RDF
11	Mohammad Redwan Islam, Susmita Karmaker, Md. Abrar Ibtesham, Irfan Rahman	A Novel Low Power Single Bit SRAM Cell Using Quasi-Adiabatic Logic.	ICECS 2022	2022	DBLP DOI BibTeX RDF
11	Dengfeng Wanq, Zhi Li, Chengjun Chang, Weifeng He, Yanan Sun 0003	All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations.	ICTA	2022	DBLP DOI BibTeX RDF
11	Tianqi Xu, Shumeng Li, Fukun Su, Xian Tang	A Current Domain Computing-in-Memory SRAM Macro with Hybrid IAF-SAR ADC for Signal Margin Enhancement.	ICTA	2022	DBLP DOI BibTeX RDF
11	Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang 0001	A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations.	ICTA	2022	DBLP DOI BibTeX RDF
11	Mridula Prathapan, Peter Mueller, Christian Menolfi, Matthias Brändli, Marcel A. Kossel, Pier Andrea Francese, David Heim, Maria Vittoria Oropallo, Andrea Ruffino, Cezar B. Zota, Thomas Morf	A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control.	ESSCIRC	2022	DBLP DOI BibTeX RDF
11	Amitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang 0069, Jae-Sun Seo, Deliang Fan	A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm.	ESSCIRC	2022	DBLP DOI BibTeX RDF
11	Adrian Kneip, Martin Lefebvre 0002, Julien Verecken, David Bol	A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization.	ESSCIRC	2022	DBLP DOI BibTeX RDF