Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs.	CHES	2003	DBLP DOI BibTeX RDF
8	Siddika Berna Örs, Elisabeth Oswald, Bart Preneel	Power-Analysis Attacks on an FPGA - First Experimental Results.	CHES	2003	DBLP DOI BibTeX RDF
8	J. L. Silva, R. M. Costa, G. H. R. Jorge	RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-Chip.	IWSOC	2003	DBLP DOI BibTeX RDF
8	Philip Heng Wai Leong, Ivan K. H. Leung	A microcoded elliptic curve processor using FPGA technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
8	Shantanu Dutt, Vinay Verma, Hasan Arslan	A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Bump-and-refit (B&R) paradigm, ECO (engineering change order), bumping cost, incremental routing, switchbox, field programmable gate arrays, dynamic programming, global routing, detailed routing
8	Jhing-Fa Wang, Jia-Ching Wang, Han-Chiang Chen, Tai-Lung Chen, Chin-Chan Chang, Ming-Chi Shih	Chip design of portable speech memopad suitable for persons with visual disabilities.	IEEE Trans. Speech Audio Process.	2002	DBLP DOI BibTeX RDF
8	William Chow, Jonathan Rose	EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits.	FPGA	2002	DBLP DOI BibTeX RDF	event horizon, manual placement and pipelining, FPGA, programmable logic
8	Oswaldo Cadenas, Graham M. Megson	Improving mW/MHz Ratio in FPGAs Pipelined Designs.	DSD	2002	DBLP DOI BibTeX RDF
8	Martyn Edwards, Benjamin Fozard	Rapid Prototyping of Mixed Hardware and Software Systems.	DSD	2002	DBLP DOI BibTeX RDF
8	Francisco Cardells-Tormo, Javier Valls-Coquillat	High Performance Quadrature Digital Mixers for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
8	Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo	Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology.	FPL	2002	DBLP DOI BibTeX RDF
8	Miguel Arias-Estrada, Eduardo Rodríguez-Palacios	An FPGA Co-processor for Real-Time Visual Tracking.	FPL	2002	DBLP DOI BibTeX RDF
8	Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo	A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations.	FPL	2002	DBLP DOI BibTeX RDF
8	Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell	Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models.	FPL	2002	DBLP DOI BibTeX RDF
8	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland	Implementing Asynchronous Circuits on LUT Based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
8	Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier	Integration of Reconfigurable Hardware into System-Level Design.	FPL	2002	DBLP DOI BibTeX RDF
8	Maya B. Gokhale, Dave Dubois, Andy Dubois, Mike Boorman, Steve Poole 0001, Vic Hogsett	Granidt: Towards Gigabit Rate Network Intrusion Detection Technology.	FPL	2002	DBLP DOI BibTeX RDF
8	Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert 0001	Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations.	FPL	2002	DBLP DOI BibTeX RDF
8	Gordon J. Brebner	Multithreading for Logic-Centric Systems.	FPL	2002	DBLP DOI BibTeX RDF
8	Kurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip Heng Wai Leong	An FPGA Based SHA-256 Processor.	FPL	2002	DBLP DOI BibTeX RDF
8	Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre, Vicente Torres-Carot	Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard.	FPL	2002	DBLP DOI BibTeX RDF
8	Tomoyoshi Kobori, Tsutomu Maruyama	High Speed Computation of Three Dimensional Cellular Automata with FPGA.	FPL	2002	DBLP DOI BibTeX RDF
8	Ivo Bolsens	Challenges and Opportunities for FPGA Platforms.	FPL	2002	DBLP DOI BibTeX RDF
8	Théodore Marescaux, T. Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins	Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
8	Kai-Pui Lam, Sui-Tung Mak	On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach.	FPL	2002	DBLP DOI BibTeX RDF
8	Richard H. Turner, Roger F. Woods, Tim Courtney	Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
8	Antti Hämäläinen, Matti Tommiska, Jorma Skyttä	8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm.	FPL	2002	DBLP DOI BibTeX RDF
8	Edson L. Horta, Sergio Takeo Kofuji	A Run-Time Reconfigurable ATM Switch.	IPDPS	2002	DBLP DOI BibTeX RDF	Partial RTR, ATM Switch, Reconfigurable Logic
8	Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell	Implementing a Simple Continuous Speech Recognition System on an FPGA.	FCCM	2002	DBLP DOI BibTeX RDF
8	Marc Necker, Didier Contis, David E. Schimmel	TCP-Stream Reassembly and State Tracking in Hardware.	FCCM	2002	DBLP DOI BibTeX RDF
8	Henry Styles, Wayne Luk	Accelerating Radiosity Calculations Using Reconfigurable Platforms.	FCCM	2002	DBLP DOI BibTeX RDF
8	Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong	A Massively Parallel RC4 Key Search Engine.	FCCM	2002	DBLP DOI BibTeX RDF
8	Jörn Gause, Peter Y. K. Cheung, Wayne Luk	Reconfigurable Shape-Adaptive Template Matching Architectures.	FCCM	2002	DBLP DOI BibTeX RDF
8	Thomas W. Fry, Scott Hauck	Hyperspectral Image Compression on Reconfigurable Platforms.	FCCM	2002	DBLP DOI BibTeX RDF
8	Tim Grembowski, Roar Lien, Kris Gaj, Nghi Nguyen, Peter Bellows, Jaroslav Flidr, Tom Lehman, Brian Schott	Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512.	ISC	2002	DBLP DOI BibTeX RDF
8	Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier	System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
8	Francisco Cardells-Tormo, A. Valls-Coquillat	Optimized FPGA-implementation of quadrature DDS.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
8	Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale	Power analysis of multiplier blocks.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
8	Yi Yang, Chunyan Wang 0004, M. Omair Ahmad, M. N. S. Swamy	An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
8	Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis	Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller.	IOLTW	2002	DBLP DOI BibTeX RDF
8	Mehboob Alam, Wael M. Badawy, Graham A. Jullien	A Novel Pipelined Threads Architecture for AES Encryption Algorithm.	ASAP	2002	DBLP DOI BibTeX RDF
8	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	A New Functional Fault Model for FPGA Application-Oriented Testing.	DFT	2002	DBLP DOI BibTeX RDF
8	Alexander H. Jackson, Andrew M. Tyrrell	Implementing Asynchronous Embryonic Circuits using AARDVArc.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
8	Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi	A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs.	IWDC	2002	DBLP DOI BibTeX RDF
8	Srihari Cadambi, Chandra Mulpuri, Pranav Ashar	A fast, inexpensive and scalable hardware acceleration technique for functional simulation.	DAC	2002	DBLP DOI BibTeX RDF	FPGA, hardware acceleration, VLIW, functional simulation
8	Jinghuan Chen, Jaekyun Moon, Kia Bazargan	A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator.	DAC	2002	DBLP DOI BibTeX RDF
8	Philip Heng Wai Leong, Chiu-Wing Sham, W. C. Wong, H. Y. Wong, Wing Seung Yuen, Monk-Ping Leong	A bitstream reconfigurable FPGA implementation of the WSAT algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
8	David R. Martinez, Tyler J. Moeller, Ken Teitelbaum	Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	VLSI rader signal processor, front end high performance filtering, digital filtering mapped to reconfigurable computing, commercial FPGA hardware, reconfigurable hardware
8	Peter McCurry, Fearghal Morgan, Liam Kilmartin	Xilinx FPGA implementation of an image classifier for object detection applications.	ICIP (3)	2001	DBLP DOI BibTeX RDF
8	Greg Snider, Barry Shackleford, Richard J. Carter	Attacking the semantic gap between application programming languages and configurable hardware.	FPGA	2001	DBLP DOI BibTeX RDF
8	Janette Frigo, Maya B. Gokhale, Dominique Lavenier	Evaluation of the streams-C C-to-FPGA compiler: an applications perspective.	FPGA	2001	DBLP DOI BibTeX RDF	FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler
8	Pawel Chodowiec, Po Khuon, Kris Gaj	Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining.	FPGA	2001	DBLP DOI BibTeX RDF	fast architectures, secret-key ciphers, pipelining, AES
8	Marek Gorgon, Jaromir Przybylo	FPGA Based Controller for Heterogeneous Image Processing System.	DSD	2001	DBLP DOI BibTeX RDF
8	Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif	Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor.	DSD	2001	DBLP DOI BibTeX RDF
8	Michael J. Wirthlin, Brian McMurtrey	Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures.	FPL	2001	DBLP DOI BibTeX RDF
8	Tilman Neumann, Andreas Koch	A Generic Library for Adaptive Computing Environments.	FPL	2001	DBLP DOI BibTeX RDF
8	Abbes Amira, Ahmed Bouridane, Peter Milligan	Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing.	FPL	2001	DBLP DOI BibTeX RDF
8	Scott McMillan, Cameron Patterson	JBitsTM Implementations of the Advanced Encryption Standard (Rijndael).	FPL	2001	DBLP DOI BibTeX RDF
8	Albert Simpson, Jill K. Hunter, Moira Wylie, Yi Hu, David Mann	Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing.	FPL	2001	DBLP DOI BibTeX RDF
8	Nikolaus Voß, Bärbel Mertsching	Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware.	FPL	2001	DBLP DOI BibTeX RDF
8	Florent de Dinechin, Arnaud Tisserand	Some Improvements on Multipartite Table Methods .	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
8	Sven E. Eklund	A Massively Parallel Architecture for Linear Machine Code Genetic Programming.	ICES	2001	DBLP DOI BibTeX RDF
8	Alexander H. Jackson, Andrew M. Tyrrell	Asynchronous Embryonics with Reconfiguration.	ICES	2001	DBLP DOI BibTeX RDF
8	Koen Claessen, Mary Sheeran, Satnam Singh	The Design and Verification of a Sorter Core.	CHARME	2001	DBLP DOI BibTeX RDF
8	Amar Mukherjee, Nitin Motgi, Jürgen Becker 0001, A. Friebe, C. Habermann, Manfred Glesner	Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
8	Anatoli Sergyienko, Oleg Maslennikov	Implementation of Givens QR-Decomposition in FPGA.	PPAM	2001	DBLP DOI BibTeX RDF
8	Kamal Rajagopalan, Peter R. Sutton	A flexible multiplication unit for an FPGA logic block.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
8	Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu	Design and implementation of channel equalizers for block transmission systems.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
8	Kris Gaj, Pawel Chodowiec	Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays.	CT-RSA	2001	DBLP DOI BibTeX RDF
8	Pauline C. Haddow, Gunnar Tufte	Bridging The Genotype-Phenotype Mapping For Digital Fpgas.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
8	Alexander H. Jackson, Andrew M. Tyrrell	Asynchronous Embryonics.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
8	Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong, Monk-Ping Leong	Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA.	CHES	2001	DBLP DOI BibTeX RDF	performance-tradeoffs, reconfigurable-computing, digital-design, Cryptographic hardware
8	Vijay Lakamraju, Russell Tessier	Tolerating operational faults in cluster-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
8	Ali M. Shankiti, Miriam Leeser	Implementing a RAKE receiver for wireless communications on an FPGA-based computer system.	FPGA	2000	DBLP DOI BibTeX RDF	FPGA, wireless communications, RAKE receiver
8	Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino	High Speed Computation of Lattice gas Automata with FPFA.	FPL	2000	DBLP DOI BibTeX RDF
8	Arran Derbyshire, Wayne Luk	Combining Serialisation and Reconfiguration for FPGA Designs.	FPL	2000	DBLP DOI BibTeX RDF
8	Kiran Bondalapati, Viktor K. Prasanna	Loop Pipelining and Optimization for Run Time Reconfiguration.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
8	Eric Keller	JRoute: A Run-Time Routing API for FPGA Hardware.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
8	Simon Perkins, Reid B. Porter, Neal R. Harvey	Everything on the Chip: A Hardware-Based Self-Contained Spatially-Structured Genetic Algorithm for Signal Processing.	ICES	2000	DBLP DOI BibTeX RDF
8	Henry Styles, Wayne Luk	Customizing Graphics Applications: Techniques and Programming Interface.	FCCM	2000	DBLP DOI BibTeX RDF
8	Monk-Ping Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong	A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA.	FCCM	2000	DBLP DOI BibTeX RDF
8	Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo	Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation.	ISSS	2000	DBLP DOI BibTeX RDF
8	Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Daniel Massicotte	Automatic Design of VLSI Pipelined LMS Architectures.	PARELEC	2000	DBLP DOI BibTeX RDF
8	Kazimierz Wiatr, Ernest Jamro	Constant Coefficient Multiplication in FPGA Structures.	EUROMICRO	2000	DBLP DOI BibTeX RDF
8	Lörinc Antoni, Régis Leveugle, Béla Fehér	Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.	DFT	2000	DBLP DOI BibTeX RDF
8	Dan Benyamin, John D. Villasenor, Wayne Luk	Optimizing FPGA-Based Vector Product Designs.	FCCM	1999	DBLP DOI BibTeX RDF	vector product, FPGA, filters, DSP
8	Tyler J. Moeller, David R. Martinez	Field Programmable Gate Array Based Radar Front-End Digital Signal Processing.	FCCM	1999	DBLP DOI BibTeX RDF
8	Delon Levi, Steve Guccione	GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF