Search results for "adder"

Hits ?▲	Authors	Title	Venue	Year	Link
13	David Gerd Woog	Inductive Adder for the FCC Injection Kicker System.		2020	RDF
13	Bharat Garg, G. K. Sharma 0001	A process-tolerant low-power adder architecture for image processing applications.	Turkish J. Electr. Eng. Comput. Sci.	2019	DBLP DOI BibTeX RDF
13	R. Arun Sekar, S. Sasipriya	Implementation of FIR filter using reversible modified carry select adder.	Concurr. Comput. Pract. Exp.	2019	DBLP DOI BibTeX RDF
13	N. Suresh Kumar, Paramasivam K	Energy efficient low-power full-adder by 65 nm CMOS technology in ALU.	Concurr. Comput. Pract. Exp.	2019	DBLP DOI BibTeX RDF
13	Komal Nain Sukhia, Muhammad Mohsin Riaz, Abdul Ghafoor	Content-based blur image retrieval using quaternion approach and frequency adder LBP.	Multidimens. Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
13	Junjun Hu, Zhijing Li 0002, Meng Yang, Zixin Huang, Weikang Qian	A high-accuracy approximate adder with correct sign calculation.	Integr.	2019	DBLP DOI BibTeX RDF
13	Gnanambikai Palanisamy, Vijeyakumar Krishnasamy Natarajan, Kalaiselvi Sundaram	Area-efficient parallel adder with faithful approximation for image and signal processing applications.	IET Image Process.	2019	DBLP DOI BibTeX RDF
13	Gongzhi Liu, Lijing Zheng, Guangyi Wang, Yiran Shen 0002, Yan Liang 0005	A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit.	IEEE Access	2019	DBLP DOI BibTeX RDF
13	Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa	Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
13	Ulrich Brenner, Anna Hermann	Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times.	ACM Trans. Algorithms	2019	DBLP DOI BibTeX RDF
13	Toshinori Sato, Tongxin Yang, Tomoaki Ukezono	Trading Accuracy for Power with a Configurable Approximate Adder.	IEICE Trans. Electron.	2019	DBLP DOI BibTeX RDF
13	Krishnan Thiruvenkadam, Jayabalan Ramesh, Anjali S. Pillai	Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
13	Esmail Roosta, Seied Ali Hosseini	A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
13	Somayeh Timarchi, Negar Akbarzadeh	Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n - 1 Adder and Multiplier.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
13	Kishore Sanapala, Ramachandran Sakthivel	Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
13	Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa	New energy-efficient hybrid wide-operand adder architecture.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
13	Elena Egorova, Marcel Fernandez, Grigory Kabatiansky, Moon Ho Lee	Signature codes for weighted noisy adder channel, multimedia fingerprinting and compressed sensing.	Des. Codes Cryptogr.	2019	DBLP DOI BibTeX RDF
13	Nobutaka Kito, Naofumi Takagi	Concurrent Error Detectable Carry Select Adder with Easy Testability.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
13	Alberto Nannarelli	Tunable Floating-Point Adder.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
13	Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy	High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
13	K. Murugan, S. Baulkani	VLSI implementation of ultra power optimized adiabatic logic based full adder cell.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
13	K. B. Bavithra, R. Siva Kumar	High throughput K best MIMO detector using modified final selector based carry select adder.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
13	Rohan Pinto, Kumara Shama	Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
13	Vinay Kumar, Ankit Singh, Shubham Upadhyay, Binod Kumar 0001	Power-Delay-Error-Efficient Approximate Adder for Error-Resilient Applications.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
13	Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj	A low leakage TG-CNTFET-based inexact full adder for low power image processing applications.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
13	S. Geetha 0002, P. Amritvalli	Design of High Speed Error Tolerant Adder Using Gate Diffusion Input Technique.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
13	Mohd Ziauddin Jahangir, J. Mounika	Design and simulation of an innovative CMOS ternary 3 to 1 multiplexer and the design of ternary half adder using ternary 3 to 1 multiplexer.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
13	Li Luo, Zhe Chen, Xinghua Yang, Fei Qiao, Qi Wei 0001, Huazhong Yang	A single clock cycle approximate adder with hybrid prediction and error compensation methods.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
13	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results.	CoRR	2019	DBLP BibTeX RDF
13	Jinping Fan, Yujie Gu, Masahiro Hachimori, Ying Miao 0001	Signature codes for weighted binary adder channel and multimedia fingerprinting.	CoRR	2019	DBLP BibTeX RDF
13	Aida Ghorbani Asibelagh, Reza Faghih Mirzaee	Applicability of Partial Ternary Full Adder in Ternary Arithmetic Units.	CoRR	2019	DBLP BibTeX RDF
13	Qi Wang 0070, Roman Verba, Thomas Brächer, Philipp Pirro, Andrii V. Chumak	Integrated magnonic half-adder.	CoRR	2019	DBLP BibTeX RDF
13	Projjal Gupta	4-Bit High-Speed Binary Ling Adder.	CoRR	2019	DBLP BibTeX RDF
13	P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis	Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder.	CoRR	2019	DBLP BibTeX RDF
13	Duggirala Meher Krishna, Duggirala Ravi	Fast Parallel Integer Adder in Binary Representation.	CoRR	2019	DBLP BibTeX RDF
13	R. Nirmaladevi, R. Seshasayanan	Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
13	Basant Kumar Mohanty	Efficient Fixed-Width Adder-Tree Design.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
13	Sally Ahmed, Saad Ilyas, Xuecui Zou, Nizar Jaber, Mohammad I. Younis, Hossein Fariborzi	A Compact Adder and Reprogrammable Logic Gate Using Micro-Electromechanical Resonators With Partial Electrodes.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
13	Julio Villalba, Javier Hormigo, Sonia González-Navarro	Fast HUB Floating-Point Adder for FPGA.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
13	Tingting Zhang, Vikramkumar Pudi, Weiqiang Liu 0001	New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
13	Haroon Waris, Chenghua Wang, Weiqiang Liu 0001	High-performance approximate half and full adder cells using NAND logic gate.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
13	Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.	Design and Analysis of Energy Efficient Reversible Logic based Full Adder.	MWSCAS	2019	DBLP DOI BibTeX RDF
13	Kyle Price, James E. Stine	Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures.	MWSCAS	2019	DBLP DOI BibTeX RDF
13	Mayank Palaria, Sai Sanjeet, Bibhu Datta Sahoo 0002, Masahiro Fujita	Adder-Only Convolutional Neural Network with Binary Input Image.	MWSCAS	2019	DBLP DOI BibTeX RDF
13	Shenghou Ma, Paul Ampadu	Optimal SAT-based Minimum Adder Synthesis of Linear Transformations.	MWSCAS	2019	DBLP DOI BibTeX RDF
13	Yu-Chen Lin, Yi-Te Hsu, Szu-Wei Fu, Yu Tsao 0001, Tei-Wei Kuo	IA-NET: Acceleration and Compression of Speech Enhancement Using Integer-Adder Deep Neural Network.	INTERSPEECH	2019	DBLP DOI BibTeX RDF
13	Nancy S. Soliman, Mohammed E. Fouda, Lobna A. Said, Ahmed H. Madian, Ahmed G. Radwan	N-digits Ternary Carry Lookahead Adder Design.	ICM	2019	DBLP DOI BibTeX RDF
13	Brett Mathis, James E. Stine	A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter.	ISVLSI	2019	DBLP DOI BibTeX RDF
13	Xinzhe Liu, Fupeng Chen, Yajun Ha	Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree.	ISVLSI	2019	DBLP DOI BibTeX RDF
13	Ning-Chi Huang, Szu-Ying Chen, Kai-Chiang Wu	Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications.	DATE	2019	DBLP DOI BibTeX RDF
13	Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka	Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application.	PReMI (2)	2019	DBLP DOI BibTeX RDF
13	Sina Boroumand, Philip Brisk	Approximate Adder Tree Synthesis for FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
13	Xinya Lei, Ruixin Guo, Feng Zhang 0012, Lizhe Wang 0001, Rui Xu, Guangzhi Qu	Accelerating Homomorphic Full Adder Based on FHEW Using Multicore CPU and GPUs.	HPCC/SmartCity/DSS	2019	DBLP DOI BibTeX RDF
13	Shan Lu 0003, Wei Hou, Jun Cheng 0001, Hiroshi Kamabe	Multi-User UD k-Ary Codes Recursively Constructed from Short-Length Multiary Codes for Multiple-Access Adder Channel.	ISIT	2019	DBLP DOI BibTeX RDF
13	Lavanya Maddisetti, J. V. R. Ravindra	Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters.	NORCAS	2019	DBLP DOI BibTeX RDF
13	Kumar Sambhav Pandey, B. Dinesh Kumar 0001, Neeraj Goel, Hitesh Shrimali	An Ultra-Fast Parallel Prefix Adder.	ARITH	2019	DBLP DOI BibTeX RDF
13	Chandan Kumar Jha 0001, Ankita Nandi, Joycee Mekie	Quality Tunable Approximate Adder for Low Energy Image Processing Applications.	ICECS	2019	DBLP DOI BibTeX RDF
13	Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah	MRL Crossbar-Based Full Adder Design.	ICECS	2019	DBLP DOI BibTeX RDF
13	Hui Yang, Shukai Duan, Lidan Wang 0001	A Novel Memristor-CMOS Hybrid Full-Adder and Its Application.	ISNN (2)	2019	DBLP DOI BibTeX RDF
13	Guilherme Paim, Leandro M. G. Rocha, Eduardo Antônio César da Costa, Sergio Bampi	Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors.	NEWCAS	2019	DBLP DOI BibTeX RDF
13	Bhaskara Rao Doddi, V. Leela Rani	Review and Implementation of 1-Bit Adder in CMOS and Hybrid Structures.	IBICA	2019	DBLP DOI BibTeX RDF
13	Tasneem AlSalem, Lina Nazzal, Marah Samara, Mawahib Hussein Sulieman	Design and Simulation of 90 nm Threshold Logic Carry-Look-Ahead Adder.	ACIT	2019	DBLP DOI BibTeX RDF
13	Rahul Singhal, Marek A. Perkowski	Comparative Analysis of Full Adder Custom Design Circuit using Two Regular Structures in Quantum-Dot Cellular Automata (QCA).	ISMVL	2019	DBLP DOI BibTeX RDF
13	Yibo Fan, Jiro Katto, Heming Sun, Xiaoyang Zeng, Yixuan Zeng	A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard.	SoCC	2019	DBLP DOI BibTeX RDF
13	Chunmei Yang, Hailong Jiao	Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations.	ICICDT	2019	DBLP DOI BibTeX RDF
13	Brett Mathis, James E. Stine	A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter.	ASAP	2019	DBLP DOI BibTeX RDF
13	Zongxian Yang, Yixiao Ma, Lan Wei	Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
13	Xiaotian Zhang, Pengjun Wang, Yunfei Yu, Yuejun Zhang, Shunxin Ye	A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback.	ASICON	2019	DBLP DOI BibTeX RDF
13	Jinghao Ye, Masao Yanagisawa, Youhua Shi	An Adder-Segmentation-based FIR for High Speed Signal Processing.	ASICON	2019	DBLP DOI BibTeX RDF
13	Jayashree K. G, Lois Priscilla S, Bhuvana B. P., V. S. Kanchana Bhaaskaran	Design and Analysis of FinFET Based CSCPAL Low Power Adder.	iSES	2019	DBLP DOI BibTeX RDF
13	Sujit Kumar Patel, Bharat Garg, Anurag Mahajan, Shireesh Kumar Rai	Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems.	iSES	2019	DBLP DOI BibTeX RDF
13	Bharat Garg, Yashoda Bisht	A Novel High Performance Reverse Carry Propagate Adder for Energy Efficient Multimedia Applications.	iSES	2019	DBLP DOI BibTeX RDF
13	Hyounghun Joe, Cheolsoo Park, Hyungtak Kim, Youngmin Kim	Lower-part Stochastic Unipolar Adder to Improve Computation Accuracy.	ISOCC	2019	DBLP DOI BibTeX RDF
13	Marshal Raj, Raja Sekar Kumaresan, Gopalakrishnan Lakshminarayanan	High Speed Controllable Inverter for Adder-Subtractor in QCA.	ICCCNT	2019	DBLP DOI BibTeX RDF
13	Mehedi Hasan, Uttam Kumar Saha, Afran Sorwar, Md. Ashik Zafar Dipto, Muhammad Saddam Hossain, Hasan U. Zaman	A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic.	ICCCNT	2019	DBLP DOI BibTeX RDF
13	Mehedi Hasan, Parag Biswas, Md. Shihabul Alam, Hasan U. Zaman, Mainul Hossain, Sharnali Islam	High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder.	ICCCNT	2019	DBLP DOI BibTeX RDF
13	Tuaha Nomani, Mujahid Mohsin	A Novel Approximate Adder Design Methodology with Single LUT Delay for Fault-tolerant FPGA-based Systems.	INTELLECT	2019	DBLP DOI BibTeX RDF
13	Bogdan Reznychenko, Yossi Paltiel, Françoise Remacle, Marinella Striccoli, Emmanuel Mazer, Maurizio Coden, Elisabetta Collini, Carlo Nazareno DiBenedetto, Ariela Donval, Barbara Fresch, Hugo Gattuso, Noam Gross	An n-Bit Adder Realized via Coherent Optical Parallel Computing.	ICRC	2019	DBLP DOI BibTeX RDF
13	Sara Ghafari, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi	A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method.	MIXDES	2019	DBLP DOI BibTeX RDF
13	Sayantani Roy, Arighna Deb, Debesh K. Das	Delay Efficient All Optical Carry Lookahead Adder.	VDAT	2019	DBLP DOI BibTeX RDF
13	Moumita Acharya, Samik Basu 0003, Biranchi Narayan Behera, Amlan Chakrabarti	Approximate Computing Based Adder Design for DWT Application.	VDAT	2019	DBLP DOI BibTeX RDF
13	Jinghao Ye, Masao Yanagisawa, Youhua Shi	A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing.	APCCAS	2019	DBLP DOI BibTeX RDF
13	D. Naveen Sai, G. Surya Kranth, Damarla Paradhasaradhi, R. S. Ernest Ravindran, M. Lakshmana Kumar, K. Mariya Priyadarshini	Five Input Multilayer Full Adder by QCA Designer.	ICACDS (2)	2019	DBLP DOI BibTeX RDF
13	Mohamed Abouzied, Hatem Osman, Vaibhav A. Vaidya, Krishnan Ravichandran, Edgar Sánchez-Sinencio	An Integrated Concurrent Multiple-Input Self-Startup Energy Harvesting Capacitive-Based DC Adder Combiner.	IEEE Trans. Ind. Electron.	2018	DBLP DOI BibTeX RDF
13	V. R. Vijaykumar, S. Raja Sekar, Elango Sekar, S. Ramakrishnan 0004	Implementation of 2n-2k-1 Modulo Adder Based RFID Mutual Authentication Protocol.	IEEE Trans. Ind. Electron.	2018	DBLP DOI BibTeX RDF
13	Alireza Andalib	A novel proposal for all-optical Galois field adder based on photonic crystals.	Photonic Netw. Commun.	2018	DBLP DOI BibTeX RDF
13	Mona Neisy, Mohammad Soroosh, Karim Ansari-Asl	All optical half adder based on photonic crystal resonant cavities.	Photonic Netw. Commun.	2018	DBLP DOI BibTeX RDF
13	Mohammad Reza Jalali-Azizpoor, Mohammad Soroosh, Yousef Seifi Kavian	Application of self-collimated beams in realizing all-optical photonic crystal-based half-adder.	Photonic Netw. Commun.	2018	DBLP DOI BibTeX RDF
13	Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot	High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression.	ACM Trans. Reconfigurable Technol. Syst.	2018	DBLP DOI BibTeX RDF
13	Mohammad Mehdi Panahi, Omid Hashemipour, Keivan Navi	A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates.	Integr.	2018	DBLP DOI BibTeX RDF
13	Masoud Pashaeifar, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
13	Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu	A Simple Yet Efficient Accuracy-Configurable Adder Design.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
13	Hamed Naseri, Somayeh Timarchi	Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
13	Saeed Rasouli Heikalabad, Mazaher Naji Asfestani, Mehdi Hosseinzadeh 0001	A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis.	J. Supercomput.	2018	DBLP DOI BibTeX RDF
13	Lei Wang 0141, Guangjun Xie	Novel designs of full adder in quantum-dot cellular automata technology.	J. Supercomput.	2018	DBLP DOI BibTeX RDF
13	Shiva Rahbar Arabani, Mohammad Reza Reshadinezhad, Majid Haghparast	Design of a parity preserving reversible full adder/subtractor circuit.	Int. J. Comput. Intell. Stud.	2018	DBLP DOI BibTeX RDF
13	Stephan Held, Sophie Theresa Spirkl	Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two.	ACM Trans. Algorithms	2018	DBLP DOI BibTeX RDF
13	Chunhui Pan, Hao San	A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer.	IEICE Trans. Electron.	2018	DBLP DOI BibTeX RDF
13	Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani	Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
13	Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi	Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF