Search results for "gate-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Paul Zuber, Armin Windschiegl, Raúl Medina Beltrán de Otálora, Walter Stechele, Andreas Herkersdorf	Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization.	DATE	2005	DBLP DOI BibTeX RDF
6	Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers	High Level Synthesis of Timed Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
6	Ho Fai Ko, Qiang Xu 0001, Nicola Nicolici	Register-transfer level functional scan for hierarchical designs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
6	Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang	Power estimation starategies for a low-power security processor.	ASP-DAC	2005	DBLP DOI BibTeX RDF
6	Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard	SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	high-level synthesis, memory synthesis
6	Bernhard Peischl, Franz Wotawa	Error traces in model-based debugging of hardware description languages.	AADEBUG	2005	DBLP DOI BibTeX RDF	conditional dependency, error trace, potential influence, fault localization, automated debugging, software debugging, source-level debugging
6	Behnam Amelifard, Ali Afzali-Kusha, Ahmad Khademzadeh	Enhancing the efficiency of cluster voltage scaling technique for low-power application.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
6	Marong Phadoongsidhi, Kewal K. Saluja	SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
6	Pallav Gupta, Niraj K. Jha	An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology.	DATE	2004	DBLP DOI BibTeX RDF
6	Markus Wedler, Dominik Stoffel, Wolfgang Kunz	Exploiting state encoding for invariant generation in induction-based property checking.	ASP-DAC	2004	DBLP DOI BibTeX RDF
6	Ozgur Sinanoglu, Alex Orailoglu	Efficient RT-level fault diagnosis methodology.	ASP-DAC	2004	DBLP DOI BibTeX RDF
6	Laurence Tianruo Yang, Jon C. Muzio	Testing Methodologies for Embedded Systems and Systems-on-Chip.	ICESS	2004	DBLP DOI BibTeX RDF
6	Tetsuya Higchi	Industrial Applications of Evolvable Hardware.	KES	2004	DBLP DOI BibTeX RDF
6	Ho Fai Ko, Nicola Nicolici	Functional Illinois Scan Design at RTL.	ICCD	2004	DBLP DOI BibTeX RDF
6	Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris	Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.	MTV	2003	DBLP DOI BibTeX RDF
6	Markus Wedler, Dominik Stoffel, Wolfgang Kunz	Using RTL Statespace Information and State Encoding for Induction Based Property Checking.	DATE	2003	DBLP DOI BibTeX RDF
6	David Andrews 0001, Douglas Niehaus	Architectural Frameworks for MPP Systems on a Chip.	IPDPS	2003	DBLP DOI BibTeX RDF	thread programming, FPGA, embedded systems, reconfigurable architectures, computational frameworks
6	Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris	Extraction Error Diagnosis and Correction in High-Performance Designs.	ITC	2003	DBLP DOI BibTeX RDF
6	Sergio Saponara, Luca Fanucci, Luca Serafini	Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL Modem.	IWSOC	2003	DBLP DOI BibTeX RDF
6	G. D. Nagendra, V. G. Prem Kumar, B. S. Sheshadri Chakravarthy	Simulation bridge: a framework for multi-processor simulation.	CODES	2002	DBLP DOI BibTeX RDF	simulation framework, instruction set simulator, multiprocessor simulation
6	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	A New Functional Fault Model for FPGA Application-Oriented Testing.	DFT	2002	DBLP DOI BibTeX RDF
6	Kenji Shimazaki, Shouzou Hirano, Hiroyuki Tsujikawa	An EMI-Noise Analysis on LSI Design with Impedance Estimation.	ISQED	2002	DBLP DOI BibTeX RDF
6	Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu	Automated timing model generation.	DAC	2002	DBLP DOI BibTeX RDF	EDA, static timing analysis, model generation
6	Subodh Gupta, Farid N. Najm	Power modeling for high-level power estimation.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
6	Wen-Chang Yeh, Chein-Wei Jen	High-Speed Booth Encoded Parallel Multiplier Design.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding
6	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
6	Subodh Gupta, Farid N. Najm	Analytical models for RTL power estimation of combinational andsequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
6	Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski	Retiming-based factorization for sequential logic optimization.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	finite stat machines, retiming, sequential synthesis
6	Carl-Johan H. Seger	Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice.	CADE	2000	DBLP DOI BibTeX RDF
6	Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino	Power Macromodeling for a High Quality RT-Level Power Estimation.	ISQED	2000	DBLP DOI BibTeX RDF
6	Alberto Nannarelli, Tomás Lang	Low-Power Divider.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Floating-point division, low-power, digit-recurrence division
6	Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001	Extraction of functional regularity in datapath circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
6	Kenneth Y. Yun, David L. Dill	Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
6	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical test generation and design for testability methods for ASPPs and ASIPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
6	Gregory H. Chisholm, Steven T. Eckmann, Christopher M. Lain, Robert Veroff	Understanding Integrated Circuits.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
6	Eric Rotenberg	AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors.	FTCS	1999	DBLP DOI BibTeX RDF	branch prediction and value prediction, trace processors, transient faults, simultaneous multithreading, time redundancy
6	Irith Pomeranz, Sudhakar M. Reddy	Vector-Based Functional Fault Models for Delay Faults.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	functional tests, delay faults, path delay faults
6	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli	Characterization-Free Behavioral Power Modeling.	DATE	1998	DBLP DOI BibTeX RDF	Modeling, Power consumption, RTL Simulation
6	Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa	Validation of an Architectural Level Power Analysis Technique.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
6	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.	DAC	1998	DBLP DOI BibTeX RDF
6	Qinru Qiu, Qing Wu 0002, Massoud Pedram	Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics.	DAC	1998	DBLP DOI BibTeX RDF	reconfigurable computing, event-driven simulation
6	Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino	Computational Kernels and their Application to Sequential Power Optimization.	DAC	1998	DBLP DOI BibTeX RDF	system-on-chip test, testing embedded core, intellectual property test
6	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
6	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	High Quality Robust Tests for Path Delay Faults.	VTS	1997	DBLP DOI BibTeX RDF	test generation, fault modeling, delay test, robust test
6	Subodh Gupta, Farid N. Najm	Power Macromodeling for High Level Power Estimation.	DAC	1997	DBLP DOI BibTeX RDF
6	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.	DAC	1997	DBLP DOI BibTeX RDF
6	Reinhard Bündgen, Wolfgang Küchlin, Werner Lauterbach	Verification of the Sparrow Processor.	ECBS	1996	DBLP DOI BibTeX RDF	symbolic hardware simulation, equational specifications, term rewriting, Hardware verification
6	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design for testability technique for RTL circuits using control/data flow extraction.	ICCAD	1996	DBLP DOI BibTeX RDF
6	Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer	An observability-based code coverage metric for functional simulation.	ICCAD	1996	DBLP DOI BibTeX RDF	verification, code coverage, functional simulation
6	Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee	Instruction Level Power Analysis and Optimization of Software.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power software, embedded systems, low power design, embedded software, power estimation, power optimization
6	Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner	The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
6	Hakan Yalcin, John P. Hayes	Hierarchical timing analysis using conditional delays.	ICCAD	1995	DBLP DOI BibTeX RDF	Hierarchical timing analysis, conditional delays, symbolic analysis, timing modeling, path sensitization, high-level modeling
6	Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas	A method for pseudo-exhaustive test pattern generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
6	Vivek Tiwari, Sharad Malik, Andrew Wolfe	Power analysis of embedded software: a first step towards software power minimization.	ICCAD	1994	DBLP DOI BibTeX RDF
6	Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham	VLSI logic and fault simulation on general-purpose parallel computers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
6	John D. Calhoun, Franc Brglez	A framework and method for hierarchical test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
6	Robert S. Boyer, J Strother Moore	A Theorem Prover for a Computational Logic.	CADE	1990	DBLP DOI BibTeX RDF
6	Michael Zimmermann, Manfred Geilert	Generation of embedded RAMs with built-in test using object-oriented programming.	EURO-DAC	1990	DBLP DOI BibTeX RDF
6	Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima	NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I.	DAC	1990	DBLP DOI BibTeX RDF
6	Carlos Delgado Kloos	STREAM: A Scheme Language for Formally Describing Digital Circuits.	PARLE (2)	1987	DBLP DOI BibTeX RDF
5	Mohammad Tehranipoor, Farinaz Koushanfar	A Survey of Hardware Trojan Taxonomy and Detection.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	hardware Trojans, Trojan taxonomy and detection, security, design and test, ICs
5	Alireza Vahdatpour, Miodrag Potkonjak	Leakage minimization using self sensing and thermal management.	ISLPED	2010	DBLP DOI BibTeX RDF	delay, thermal management, leakage energy
5	Sina Meraji, Wei Zhang 0034, Carl Tropper	Brief announcement: a reinforcement learning approach for dynamic load-balancing of parallel digital logic simulation.	SPAA	2010	DBLP DOI BibTeX RDF	digital logic simulation, reinforcement learning, dynamic load-balancing, time warp, verilog
5	Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan	Round-level concurrent error detection applied to Advanced Encryption Standard.	DDECS	2009	DBLP DOI BibTeX RDF
5	Ivan Poliakov, Victor Khomenko, Alexandre Yakovlev	Workcraft - A Framework for Interpreted Graph Models.	Petri Nets	2009	DBLP DOI BibTeX RDF
5	Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001	A novel BIST approach for testing input/output buffers in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	i/o buffers, built-in self-test, fpga testing
5	Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara	Fast false path identification based on functional unsensitizability using RTL information.	ASP-DAC	2009	DBLP DOI BibTeX RDF
5	Qing Xu 0004, Carl Tropper	On Determining How Many Computers to Use in Parallel VLSI Simulation.	PADS	2009	DBLP DOI BibTeX RDF
5	Siddharth Garg, Diana Marculescu	3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs.	ISQED	2009	DBLP DOI BibTeX RDF
5	Suresh Raman, Mike Lubyanitsky	Cone Resynthesis ECO Methodology for Multi-Million Gate Designs.	VLSI Design	2009	DBLP DOI BibTeX RDF
5	P. Balasubramanian 0001, David A. Edwards	A New Design Technique for Weakly Indicating Function Blocks.	DDECS	2008	DBLP DOI BibTeX RDF
5	Christian Haufe, Frank Rogin	Ad-Hoc Translations to Close Verilog Semantics Gap.	DDECS	2008	DBLP DOI BibTeX RDF
5	Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee	A hybrid software-based self-testing methodology for embedded processor.	SAC	2008	DBLP DOI BibTeX RDF	embedded processor testing, fault coverage, functional testing, software-based self-test
5	Melanie Elm, Hans-Joachim Wunderlich	Scan Chain Organization for Embedded Diagnosis.	DATE	2008	DBLP DOI BibTeX RDF
5	Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang	A fast two-pass HDL simulation with on-demand dump.	ASP-DAC	2008	DBLP DOI BibTeX RDF
5	Eduardo Luis Rhod, Luigi Carro	An efficient test and characterization approach for nanowire-based architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	nanoPLA, test, yield, characterization, nanowires
5	Pradeep Fernando, Hariharan Sankaran, Srinivas Katkoori, Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Rajeshuni Ramesham	A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.	IPDPS	2008	DBLP DOI BibTeX RDF
5	Ashur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev	Conversion driven design of binary to mixed radix circuits.	ICCD	2008	DBLP DOI BibTeX RDF
5	Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee	De-synchronization of a point-of-sales digital-logic controller.	ISCAS	2008	DBLP DOI BibTeX RDF
5	Azam Beg, P. W. Chandana Prasad, Walid Ibrahim, Emad Abu Shama	Utilizing synthesis to verify Boolean function models.	ISCAS	2008	DBLP DOI BibTeX RDF
5	Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee	A hybrid self-testing methodology of processor cores.	ISCAS	2008	DBLP DOI BibTeX RDF
5	Renfei Liu, Keshab K. Parhi	Fast composite field S-box architectures for advanced encryption standard.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	advanced encryption standard (aes), composite finite field, s-box, precomputation
5	André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler	Using unsatisfiable cores to debug multiple design errors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sat-based debugging, unsatisfiable core, fault localization
5	Viswanathan Subramanian, Arun K. Somani	Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
5	Xiaoji Ye, Frank Liu 0001, Peng Li 0001	Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
5	Paolo Bonzini, Dilek Harmanci, Laura Pozzi	A Study of Energy Saving in Customizable Processors.	SAMOS	2007	DBLP DOI BibTeX RDF
5	Toshinori Sato, Yuji Kunitake	Exploiting Input Variations for Energy Reduction.	PATMOS	2007	DBLP DOI BibTeX RDF	typical-case design, dynamic retiming, reliable microarchitecture, robust microarchitecture, DVFS, deep sub-micron
5	Seonyoung Lee, Kyeongsoon Cho	Design of Transform and Quantization Circuit for Multi-Standard Integrated Video Decoder.	SiPS	2007	DBLP DOI BibTeX RDF
5	Atsushi Hasegawa	Recent Trend in Industry and Expectation to DA Research.	ATVA	2007	DBLP DOI BibTeX RDF
5	Karthick Parashar, Nitin Chandrachoodan	A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation.	FPL	2007	DBLP DOI BibTeX RDF
5	Zain-ul-Abdin, Bertil Svensson	A Study of Design Efficiency with a High-Level Language for FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
5	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IPDPS	2007	DBLP DOI BibTeX RDF
5	Houjun Liang, Wenjian Luo, Xufa Wang	Designing Polymorphic Circuits with Evolutionary Algorithm Based on Weighted Sum Method.	ICES	2007	DBLP DOI BibTeX RDF	Polymorphic Circuit, Weighted Sum, Evolutionary Algorithm
5	Shanq-Jang Ruan, Wei-Te Lin	Bipartition Architecture for Low Power JPEG Huffman Decoder.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Low power, Decoding, Bipartition, Huffman
5	Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout	A nonlinear cell macromodel for digital applications.	ICCAD	2007	DBLP DOI BibTeX RDF
5	Lei Cheng 0001, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig	Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.	ICCAD	2007	DBLP DOI BibTeX RDF
5	Kundan Kumar, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury	Design of a Differential Power Analysis Resistant Masked AES S-Box.	INDOCRYPT	2007	DBLP DOI BibTeX RDF
5	Mohammad Samie, Gabriel Dragffy, Janice Kiely	Novel Embryonic Array with Neural Network Characteristics.	AHS	2007	DBLP DOI BibTeX RDF
5	Taeko Matsunaga, Yusuke Matsunaga	Area minimization algorithm for parallel prefix adders under bitwise delay constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	arithmetic synthesis, dynamic programming, parallel prefix adder
5	Zhengtao Yu 0002, Marios C. Papaefthymiou, Xun Liu	Skew spreading for peak current reduction.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	low power, clock skew, clock scheduling