Search results for "inductance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Antti Heiskanen, Timo Rahkonen	Comparison of two class E amplifiers for EER transmitter.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
10	Tadashi Suetsugu, Marian K. Kazimierczuk	Voltage-clamped class E amplifier with transmission-line transformer.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
10	H. N. Nagaraja, Amit Patra, Debaprasad Kastha	Generalized analysis of integrated magnetic component based low voltage interleaved DC-DC buck converter for efficiency improvement.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Yarallah Koolivand, Omid Shoaei, Ali Zahabi, Hossein Shamsi, Parviz Jabedar Maralani	A new technique for design CMOS LNA for multi-standard receivers.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
10	Naokazu Muramatsu, Hiroshi Okazaki, Takao Waho	A novel oscillation circuit using a resonant-tunneling diode.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Bartomeu Alorda, Sebastià A. Bota, Jaume Segura 0001	A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF	Current based testing, built-in current monitors, high-speed measurements, transient current
10	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors	Accounting for the skin effect during repeater insertion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	buffer design, optimization, delay, power, repeater insertion, skin effect
10	Amitava Bhaduri, Ranga Vemuri	Moment-driven coupling-aware routing methodology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	coupling-aware, routing, moments
10	Mikhail Popovich, Eby G. Friedman	Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems.	ISQED	2005	DBLP DOI BibTeX RDF
10	Bahar Khadem Hosseinieh, Nasser Masoumi	A Comprehensive Model for On-Chip Spiral Inductors.	IWSOC	2005	DBLP DOI BibTeX RDF
10	Rong-Jong Wai, Jeng-Dao Lee	Intelligent motion control for linear piezoelectric ceramic motor drive.	IEEE Trans. Syst. Man Cybern. Part B	2004	DBLP DOI BibTeX RDF
10	Ching-An Lin, Chien-Hsien Wu	Second-order approximations for RLC trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driver output model for on-chip RLC transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Michael I. Ferguson, Vu Duong, Xin Guo 0002	Evolvable hardware techniques for on-chip automated reconfiguration of programmable devices.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Reconfigurable chips, Programmable devices, Genetic algorithms, Evolvable hardware, Automated design
10	Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner	On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.	PATMOS	2004	DBLP DOI BibTeX RDF
10	Alain Lopez, Denis Deschacht	Comparison between Different Data Buses Configurations.	ISVLSI	2004	DBLP DOI BibTeX RDF
10	Yong Zhan, Sachin S. Sapatnekar	Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming.	DATE	2004	DBLP DOI BibTeX RDF
10	Jeffrey McFiggins, Marie Yvanoff, Jayanti Venkataraman	Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal Applications.	DSD	2004	DBLP DOI BibTeX RDF
10	Hao Ji, Qingjian Yu, Wayne Wei-Ming Dai	SPICE compatible circuit models for partial reluctance K.	ASP-DAC	2004	DBLP DOI BibTeX RDF
10	Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Accurate capture of timing parameters in inductively-coupled on-chip interconnects.	SBCCI	2004	DBLP DOI BibTeX RDF	signal delay, crosstalk, on-chip interconnects, interconnect models, inductive coupling
10	Lukasz Zielinski, Jerzy Rutkowski	Design Centering and Tolerancing with Utilization of Evolutionary Techniques.	WSC	2004	DBLP DOI BibTeX RDF
10	Federico Sandoval-Ibarra, L. Flores-Gómez	Design of Silicon-Based Suspended Inductors for UHF Applications.	CONIELECOMP	2004	DBLP DOI BibTeX RDF
10	Takao Tsuchiya, Yukio Kagawa	On the Passive Vibration Damping by Piezoelectric Transducers with Inductive Loading.	AsiaSim	2004	DBLP DOI BibTeX RDF
10	Xiuqin Chen, Shaoming Yang, M. Hasegawa, Kan Takeuchi, K. Kawabe, Seiji Motojima	Novel Tactile Sensors Manufactured by Carbon Microcoils.	ICMENS	2004	DBLP DOI BibTeX RDF
10	Olivier Duval, L.-P. Lafrance, Yvon Savaria, Patrick Desjardins	An Integrated Test Platform for Nanostructure Electrical Characterization.	ICMENS	2004	DBLP DOI BibTeX RDF
10	Imed Zine-El-Abidine, Michal M. Okoniewski, John G. McRory	A Tunable RF MEMS Inductor.	ICMENS	2004	DBLP DOI BibTeX RDF	tunable, MEMS, radio frequency, inductor
10	Alain Salles, Bruno Estibals, Corinne Alonso	Electro-thermal study of nano-inductors for integrated low power converters.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
10	Sunil Yu, Dusan Petranovic, Shoba Krishnan, Kwyro Lee, Cary Y. Yang	Resistance Matrix in Crosstalk Modeling for Muliconductor Systems.	ISQED	2004	DBLP DOI BibTeX RDF
10	Yves Quéré, Thierry LeGouguec, Pierre-Marie Martin, Fabrice Huret	Interconnect Mode Conversion in High-Speed VLSI Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
10	Li Ding 0002, Pinaki Mazumder	Simultaneous switching noise analysis using application specific device modeling.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Jérôme Lescot, François J. R. Clément	Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
10	Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni	Effects of Temperature in Deep-Submicron Global Interconnect Optimization.	PATMOS	2003	DBLP DOI BibTeX RDF
10	Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen	SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation.	ICCAD	2003	DBLP DOI BibTeX RDF
10	Kee-Keun Lee, Bruce C. Kim	MEMS Spring Probe for Next Generation Wafer Level Testing.	ICMENS	2003	DBLP DOI BibTeX RDF
10	Payman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe	A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors.	ICCD	2003	DBLP DOI BibTeX RDF
10	Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas, M. Gloanec, E. Leclerc, Bernard Lefebvre	Broad-band transimpedance amplifier for multigigabit-per-second (40 Gbps) optical communication systems in 0.135µm PHEMT technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas, M. Gloanec, E. Leclerc, Bernard Lefebvre	High gain GaAs 10Gbps transimpedance amplifier with integrated bondwire effects.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
10	Noha H. Mahmoud, Yehea I. Ismail	Accurate rise time and overshoots estimation in RLC interconnects.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Tadashi Suetsugu, Marian K. Kazimierczuk	Lossless voltage-clamping of a class E amplifier with a transformer and a diode.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
10	Robert Charles Koons, John R. Long	An inductively-tuned quadrature oscillator with extended frequency control range.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi	Noise-constrained interconnect optimization for nanometer technologies.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Nirmal K. Bose, Alfred Fettweis	Skew-symmetry in the equivalent representation problem of a time-varying multiport inductor.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
10	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect
10	Li Yang, J. S. Yuan	Analyzing Internal-Switching Induced Simultaneous Switching Noise.	ISQED	2003	DBLP DOI BibTeX RDF
10	Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail	Efficient model order reduction including skin effect.	DAC	2003	DBLP DOI BibTeX RDF	simulation, VLSI, model order reduction, skin effect, RLC
10	Rajesh Kumar 0006	Interconnect and noise immunity design for the Pentium 4 processor.	DAC	2003	DBLP DOI BibTeX RDF
10	Hao Yu 0001, Lei He 0001	Vector potential equivalent circuit based on PEEC inversion.	DAC	2003	DBLP DOI BibTeX RDF
10	Christer Svensson	Electrical interconnects revitalized.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
10	Michael W. Beattie, Lawrence T. Pileggi	On-chip induction modeling: basics and advanced methods.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
10	Yungseon Eo, Jongin Shim, William R. Eisenstadt	A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim	Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Gregorio Cappuccino, Giuseppe Cocorullo	Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Yolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho	Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics.	DATE	2002	DBLP DOI BibTeX RDF
10	Andrea Pacelli	A local circuit topology for inductive parasitics.	ICCAD	2002	DBLP DOI BibTeX RDF
10	Masaru Ogawa	Magnetizing inrush current of a transformer and a new technique of its computation.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
10	Min Zhao 0001, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal	Worst case clock skew under power supply variations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	clock skew, power supply noise, clock network
10	Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng	Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Apisak Worapishet, S. Ninyawee, Mitchai Chongcheawchamnan	Enhanced tuneable coupled inductor for ultra-wide variable centre frequency LC filters.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
10	Hui Zheng, Lawrence T. Pileggi	Modeling and analysis of regular symmetrically structured power/ground distribution networks.	DAC	2002	DBLP DOI BibTeX RDF	design tegularity, folding technique, power/ground distribution, susceptance
10	Jason Cong, Cheng-Kok Koh, Patrick H. Madden	Interconnect layout optimization under higher order RLC model forMCM designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
10	Tao Lin, Lawrence T. Pileggi	RC(L) interconnect sizing with second order considerations via posynomial programming.	ISPD	2001	DBLP DOI BibTeX RDF	RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization
10	Kenneth Rose	A comprehensive look at system level model.	SLIP	2001	DBLP DOI BibTeX RDF
10	Pietro Andreani	A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Kinya Matsuda, Yoshihiko Horio, Kazuyuki Aihara	A simulated LC oscillator using multi-input floating-gate MOSFETS.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
10	William H. Kao, Chi-Yuan Lo, Raminderpal Singh, Mark Basel	Parasitic extraction: current state of the art and future trends.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
10	Juan A. Montiel-Nelson, De de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi	A compact layout technique to minimize high frequency switching effects in high speed circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez	A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits.	ISQED	2001	DBLP DOI BibTeX RDF
10	Dingming Xie, Leonard Forbes	Phase noise on a 2-GHz CMOS LC oscillator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Dennis Sylvester, Kurt Keutzer	A global wiring paradigm for deep submicron design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.	ICCD	2000	DBLP DOI BibTeX RDF
10	Mehdi M. Mechaik	Effects of Package Stackups on Microprocessor Performance.	ISQED	2000	DBLP DOI BibTeX RDF
10	Li-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi	A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance.	ISQED	2000	DBLP DOI BibTeX RDF
10	Sanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran	Jitter Estimation Methodology for Clock Chips.	VLSI Design	2000	DBLP DOI BibTeX RDF
10	Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw	Design and Analysis of Power Distribution Networks with Accurate RLC Models.	VLSI Design	2000	DBLP DOI BibTeX RDF
10	Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh	Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks.	DAC	2000	DBLP DOI BibTeX RDF
10	Mustafa Celik, Lawrence T. Pileggi	Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
10	Yorgos Koutsoyannopoulos, Yannis Papananos, Sotiris Bantas, Carlo Alemanni	Novel Si integrated inductor and transformer structures for RF IC design.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
10	Kevin J. Kerns, Andrew T. Yang	Preservation of passivity during RLC network reduction via split congruence transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
10	Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez	A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design.	DATE	1998	DBLP DOI BibTeX RDF	Gallium Arsenide automated layout generation system, GaAs VLSI design, power supply and ground distribution model, full-custom cell layout style, full-custom layouts of very high speed circuits, cell library builder, random logic macrocell generator, iterative logic array generator
10	Lawrence T. Pileggi	Timing metrics for physical design of deep submicron technologies.	ISPD	1998	DBLP DOI BibTeX RDF
10	Payam Heydari, Massoud Pedram	Calculation of ramp response of lossy transmission lines using two-port network functions.	ISPD	1998	DBLP DOI BibTeX RDF
10	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Power dissipated by CMOS gates driving lossless transmission lines.	ISLPED	1998	DBLP DOI BibTeX RDF
10	S. R. Vemuru	Effects of simultaneous switching noise on the tapered buffer design.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
10	Qing Zhu, Wayne Wei-Ming Dai	High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
10	Kai-Yuan Chao, D. F. Wong 0001	Signal integrity optimization on the pad assignment for high-speed VLSI design.	ICCAD	1995	DBLP DOI BibTeX RDF	pad assignment, simultaneous swiching Noise, floorplanning, crosstalk, signal integrity, packaging
10	Thomas F. Hayes, John J. Barrett	Modeling of multiconductor systems for packaging and interconnecting high-speed digital IC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
10	George L. Matthaei, Gilbert C. Chinn, Charles H. Plott, Nadir Dagli	A simplified means for computation for interconnect distributed capacitances and inductances.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
10	Steven Paul McCormick, Jonathan Allen	Waveform Moment Methods for Improved Interconnection Analysis.	DAC	1990	DBLP DOI BibTeX RDF
10	Guang-Wen Pan, Kenneth S. Olson, Barry K. Gilbert	Improved algorithmic methods for the prediction of wavefront propagation behavior in multiconductor transmission lines for high frequency digital signal processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF