Search results for "DDECS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen	IP Integration Overhead Analysis in System-on-Chip Video Encoder.	DDECS	2007	DBLP DOI BibTeX RDF
1	Vytautas Dumbrava, Linas Svilainis	RF Transformer Model Parameters Measurement.	DDECS	2007	DBLP DOI BibTeX RDF
1	Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich	Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.	DDECS	2007	DBLP DOI BibTeX RDF
1	Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka	Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.	DDECS	2007	DBLP DOI BibTeX RDF
1	Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto 0001, Thomas W. Williams	Accurately Determining Bridging Defects from Layout.	DDECS	2007	DBLP DOI BibTeX RDF
1	Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino (eds.)	Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007	DDECS	2007	DBLP BibTeX RDF
1	Santiago De Pablo, Santiago Cáceres, Jesús A. Cebrián, Manuel Berrocal	A Proposal for ASM++ Diagrams.	DDECS	2007	DBLP DOI BibTeX RDF
1	Ari Kulmala, Erno Salminen, Timo D. Hämäläinen	Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder.	DDECS	2007	DBLP DOI BibTeX RDF
1	Jim Tørresen, Jorgen Norendal, Kyrre Glette	Establishing a New Course in Reconfigurable Logic System Design.	DDECS	2007	DBLP DOI BibTeX RDF
1	Sergei B. Musin, Alexander A. Ivaniuk, Vyacheslav N. Yarmolik	Multiple Errors Detection Technique for RAM.	DDECS	2007	DBLP DOI BibTeX RDF
1	Gyula Bakonyi-Kiss, Zoltán Szucs	Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive Applications.	DDECS	2007	DBLP DOI BibTeX RDF
1	Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík	Clockless Implementation of LEON2 for Low-Power Applications.	DDECS	2007	DBLP DOI BibTeX RDF
1	Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.	DDECS	2007	DBLP DOI BibTeX RDF
1	Ernest Jamro, Maciej Wielgosz, Kazimierz Wiatr	FPGA Implementation of Strongly Parallel Histogram Equalization.	DDECS	2007	DBLP DOI BibTeX RDF
1	René Kothe, Heinrich Theodor Vierhaus	Flip-Flops and Scan-Path Elements for Nanoelectronics.	DDECS	2007	DBLP DOI BibTeX RDF
1	Petr Struhovský, Ondrej Subrt, Jirí Hospodka, Pravoslav Martínek	Developing Virtual ADC Testing Environment in MAPLE.	DDECS	2007	DBLP DOI BibTeX RDF
1	Zhicheng Liang, Makoto Ikeda, Kunihiro Asada	Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology.	DDECS	2007	DBLP DOI BibTeX RDF
1	Valeria Sipala, Domenico Lo Presti, Nunzio Randazzo, Luigi Caponetto	A PMT Interface for the Optical Module Front-end of a Neutrino Underwater Telescope.	DDECS	2007	DBLP DOI BibTeX RDF
1	Roman P. Bazylevych, Ihor Podolskyy, Lubov Bazylevych	Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters.	DDECS	2007	DBLP DOI BibTeX RDF
1	Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego	An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.	DDECS	2007	DBLP DOI BibTeX RDF
1	Pavel Kubalík, Jirí Kvasnicka, Hana Kubátová	Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System.	DDECS	2007	DBLP DOI BibTeX RDF
1	Chiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo-Shing Huang	A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System.	DDECS	2007	DBLP DOI BibTeX RDF
1	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier	XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects.	DDECS	2007	DBLP DOI BibTeX RDF
1	Fabrício Vivas Andrade, Márcia C. M. Oliveira, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.	SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse.	DDECS	2007	DBLP DOI BibTeX RDF
1	Jiri Jenícek, Ondrej Novák	Test Pattern Compression Based on Pattern Overlapping.	DDECS	2007	DBLP DOI BibTeX RDF
1	Ireneusz Brzozowski, Andrzej Kos	Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.	DDECS	2007	DBLP DOI BibTeX RDF
1	Matthias Bucher, Antonios Bazigos, Wladyslaw Grabinski	Determining MOSFET Parameters in Moderate Inversion.	DDECS	2007	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev	Manifestation of Precharge Faults in High Speed DRAM Devices.	DDECS	2007	DBLP DOI BibTeX RDF
1	Jim Tørresen, Thor Arne Lovland	Parts Obsolescence Challenges for the Electronics Industry.	DDECS	2007	DBLP DOI BibTeX RDF
1	Lukás Sekanina	Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates.	DDECS	2007	DBLP DOI BibTeX RDF
1	Khalil Arshak, Francis Adepoju, Essa Jafer	Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application.	DDECS	2007	DBLP DOI BibTeX RDF
1	Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre	A Novel Parity Bit Scheme for SBox in AES Circuits.	DDECS	2007	DBLP DOI BibTeX RDF
1	Costin Cepisca, Sorin Dan Grigorescu, Mircea Covrig, Horia Andrei	About the Efficiency of Real Time Sequences FFT Computing.	DDECS	2007	DBLP DOI BibTeX RDF
1	Daniel Tille, Görschwin Fey, Rolf Drechsler	Instance Generation for SAT-based ATPG.	DDECS	2007	DBLP DOI BibTeX RDF
1	Marc Herbstritt, Bernd Becker 0001, Erika Ábrahám, Christian Herde	On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata.	DDECS	2007	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy 0001	Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.	DDECS	2007	DBLP DOI BibTeX RDF
1	Aristides Efthymiou	Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits.	DDECS	2007	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Mixed Approach for Unified Logic Diagnosis.	DDECS	2007	DBLP DOI BibTeX RDF
1	Lukas Ruckay, Jiri Nedved	Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization.	DDECS	2007	DBLP DOI BibTeX RDF
1	Wlodzimierz Jonca	Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit.	DDECS	2007	DBLP DOI BibTeX RDF
1	Manuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira 0001	A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs.	DDECS	2007	DBLP DOI BibTeX RDF
1	Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz	Power Dissipation in Basic Global Clock Distribution Networks.	DDECS	2007	DBLP DOI BibTeX RDF
1	Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng	A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing.	DDECS	2007	DBLP DOI BibTeX RDF
1	Jan Korenek, Petr Kobierský	Intrusion Detection System Intended for Multigigabit Networks.	DDECS	2007	DBLP DOI BibTeX RDF
1	Ábel Vámos	Quadrature-Phase Topology of a High Frequency Ring Oscillator.	DDECS	2007	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda	Extended Fault Detection Techniques for Systems-on-Chip.	DDECS	2007	DBLP DOI BibTeX RDF
1	Frank Rogin, Erhard Fehlauer, Christian Haufe, Sebastian Ohnewald	Debug Patterns for Efficient High-level SystemC Debugging.	DDECS	2007	DBLP DOI BibTeX RDF
1	Daniel D. Gajski	New Strategies for System-Level Design.	DDECS	2007	DBLP DOI BibTeX RDF
1	Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz	ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing.	DDECS	2007	DBLP DOI BibTeX RDF
1	Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi	A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.	DDECS	2007	DBLP DOI BibTeX RDF
1	Khalil Arshak, Essa Jafer, Christian Ibala	Power Testing of an FPGA-based System Using Modelsim Code Coverage Capability.	DDECS	2007	DBLP DOI BibTeX RDF
1	Pawel Pawlowski, Adam Dabrowski, Mario Schölzel	Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic.	DDECS	2007	DBLP DOI BibTeX RDF
1	András Timár, Márta Rencz	Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS Technology.	DDECS	2007	DBLP DOI BibTeX RDF
1	Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu	Reticle Exposure Plans for Multi-Project Wafers.	DDECS	2007	DBLP DOI BibTeX RDF
1	Thomas O. Shea, Ian Andrew Grout, Jeffrey Ryan	Memory Based Analogue Signal Generation Implementation Issues for BIST.	DDECS	2007	DBLP DOI BibTeX RDF
1	Radoslaw Czarnecki, Stanislaw Deniziak	Resource Constrained Co-synthesis of Self-reconfigurable SOPCs.	DDECS	2007	DBLP DOI BibTeX RDF
1	Pawel Russek, Kazimierz Wiatr	Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment.	DDECS	2007	DBLP DOI BibTeX RDF
1	Vladimir Havel, Karel K. Vlcek	Feasibility of Image Compression in FPGA-based Neural Networks.	DDECS	2007	DBLP DOI BibTeX RDF
1	Piotr Buciak, Jakub Botwicz	Lightweight Multi-threaded Network Processor Core in FPGA.	DDECS	2007	DBLP DOI BibTeX RDF
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Transition Faults Testing Based on Functional Delay Tests.	DDECS	2007	DBLP DOI BibTeX RDF
1	Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.	DDECS	2007	DBLP DOI BibTeX RDF
1	Tomás Martínek, Otto Fucík, Patrik Beck, Matej Lexa	Automatic Generation of Circuits for Approximate String Matching.	DDECS	2007	DBLP DOI BibTeX RDF
1	Tomasz Golonek, Damian Grzechca, Jerzy Rutkowski	Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization.	DDECS	2007	DBLP BibTeX RDF
1	Luigi Dilillo, Bashir M. Al-Hashimi	March CRF: an Efficient Test for Complex Read Faults in SRAM Memories.	DDECS	2007	DBLP DOI BibTeX RDF
1	Ketan Paranjape	Multi-Site Collaboration in System on Chip Design and Validation: The Intel Experience.	DDECS	2006	DBLP BibTeX RDF
1	Martin Stáva, Ondrej Novák	HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration.	DDECS	2006	DBLP DOI BibTeX RDF
1	Geguang Pu, Jifeng He 0001, Zongyan Qiu	An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem.	DDECS	2006	DBLP DOI BibTeX RDF
1	Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet	PE-ICE: Parallelized Encryption and Integrity Checking Engine.	DDECS	2006	DBLP DOI BibTeX RDF
1	Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg	Multiple Valued Counter.	DDECS	2006	DBLP DOI BibTeX RDF
1	Félix Tobajas, Roberto Esper-Chaín, Raúl Regidor, Octavio Santana, Roberto Sarmiento	A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology.	DDECS	2006	DBLP DOI BibTeX RDF
1	Abid Rashid, Frank H. P. Fitzek, Ole Olsen, Morten Gade, Yannick Le Moullec	A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication.	DDECS	2006	DBLP DOI BibTeX RDF
1	Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina	FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties.	DDECS	2006	DBLP DOI BibTeX RDF
1	Harri Lampinen, Pauli Perälä, Olli Vainio	Design of a Scalable Asynchronous Dataflow Processor.	DDECS	2006	DBLP DOI BibTeX RDF
1	André V. Fidalgo, Gustavo R. Alves, José M. Ferreira 0001	A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns.	DDECS	2006	DBLP DOI BibTeX RDF
1	Aki Penttinen, Rafal P. Jastrzebski, Riku Pöllänen, Olli Pyrhönen	Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor.	DDECS	2006	DBLP DOI BibTeX RDF
1	Zoran Stamenkovic, C. Wolf, Günter Schoof, Jiri Gaisler	LEON-2: General Purpose Processor for a Wireless Engine.	DDECS	2006	DBLP DOI BibTeX RDF
1	José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira 0001	Probabilistic Testability Analysis and DFT Methods at RTL.	DDECS	2006	DBLP DOI BibTeX RDF
1	Jaroslav Skarvada	Test Scheduling for SoC under Power Constraints.	DDECS	2006	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.	DDECS	2006	DBLP DOI BibTeX RDF
1	Cecilia Metra, Daniele Rossi 0001, Martin Omaña 0001, José Manuel Cazeaux, T. M. Mak	Can Clock Faults be Detected Through Functional Test?	DDECS	2006	DBLP DOI BibTeX RDF
1	György Bognár, Gyula Horváth, Zoltán Szucs, Vladimír Székely	Die Attach Quality Testing by Fully Contact-less Measurement Method.	DDECS	2006	DBLP DOI BibTeX RDF
1	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Parallel Memory Architecture for Arbitrary Stride Accesses.	DDECS	2006	DBLP DOI BibTeX RDF
1	Guoyan Zhang, Ronan Farrell	Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits.	DDECS	2006	DBLP DOI BibTeX RDF
1	Luz Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras	Lissajous Based Mixed-Signal Testing for N-Observable Signals.	DDECS	2006	DBLP DOI BibTeX RDF
1	Jiri Kadlec, Martin Danek	Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC.	DDECS	2006	DBLP DOI BibTeX RDF
1	Eric Armengaud	Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems.	DDECS	2006	DBLP DOI BibTeX RDF
1	Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu	A Switch Supporting Circuit and Packet Switching for On-Chip Networks.	DDECS	2006	DBLP DOI BibTeX RDF
1	Ondrej Subrt, Pravoslav Martínek	A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters.	DDECS	2006	DBLP DOI BibTeX RDF
1	René Kothe, Christian Galke, Sabine Schultke, Henry Fröschke, Steffen Gaede, Heinrich Theodor Vierhaus	Hardware/Software Based Hierarchical Self Test for SoCs.	DDECS	2006	DBLP DOI BibTeX RDF
1	Josef Strnadel	Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space.	DDECS	2006	DBLP DOI BibTeX RDF
1	Zbysek Gajda	A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming.	DDECS	2006	DBLP DOI BibTeX RDF
1	Pierre Vanhauwaert, Régis Leveugle, Philippe Roche	A Flexible SoPC-based Fault Injection Environment.	DDECS	2006	DBLP DOI BibTeX RDF
1	Youssef Serrestou, Vincent Beroulle, Chantal Robach	How to Improve a Set of Design Validation Data by Using Mutation-based Test.	DDECS	2006	DBLP DOI BibTeX RDF
1	Shih-Chang Hsia, Wen-Ching Lee	A New 6-bit Flash A/D Converter Using Novel Two-Step Structure.	DDECS	2006	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso	Test Considerations about the Structured ASIC Paradigm.	DDECS	2006	DBLP DOI BibTeX RDF
1	Gergely Perlaky, Gábor Mezösi, Imre Zolomy	Sensor Powering with Integrated MOS Compatible Solar Cell Array.	DDECS	2006	DBLP DOI BibTeX RDF
1	S. V. Yarmolik, Bartosz Sokol	Optimal Memory Address Seeds for Pattern Sensitive Faults Detection.	DDECS	2006	DBLP DOI BibTeX RDF
1	Piotr Dziurzanski, Wlodzimierz Bielecki, Konrad Trifunovic, M. Kleszczonek	A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description.	DDECS	2006	DBLP DOI BibTeX RDF
1	Régis Leveugle, V. Maingot	On the Use of Information Redundancy When Designing Secure Chips.	DDECS	2006	DBLP DOI BibTeX RDF
1	Grzegorz Pastuszak	Architecture Design for the Context Formatter in the H.264/AVC Encoder.	DDECS	2006	DBLP DOI BibTeX RDF

Publications at "DDECS"( http://dblp.L3S.de/Venues/DDECS )