Search results for "ISCA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger	Architecting phase change memory as a scalable dram alternative.	ISCA	2009	DBLP DOI BibTeX RDF	dram alternative, performance, scalability, power, energy, phase change memory, pcm, endurance
1	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.	ISCA	2009	DBLP DOI BibTeX RDF	bandwidth decoupling, decoupled DIMM, DRAM memories
1	Carlos Madriles, Pedro López 0001, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González 0001	Boosting single-thread performance in multi-core systems through fine-grain multi-threading.	ISCA	2009	DBLP DOI BibTeX RDF	core-fusion, single-thread performance, multicore, automatic parallelization, thread-level parallelism, speculative multithreading
1	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
1	Krishna K. Rangan, Gu-Yeon Wei, David M. Brooks	Thread motion: fine-grained power management for multi-core systems.	ISCA	2009	DBLP DOI BibTeX RDF	multi-core power management, thread motion, dvfs
1	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
1	Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
1	Katherine A. Yelick	Ten ways to waste a parallel computer.	ISCA	2009	DBLP DOI BibTeX RDF	parallel computer, energy
1	Jie Yu 0016, Satish Narayanasamy	A case for an interleaving constrained shared-memory multi-processor.	ISCA	2009	DBLP DOI BibTeX RDF	parallel programming, multiprocessors, software reliability, concurrency bugs
1	Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti	Achieving predictable performance through better memory controller placement in many-core CMPs.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, chip multiprocessors, routing algorithms, memory controllers
1	Pedro Diaz, Marcelo Cintra	Stream chaining: exploiting multiple levels of correlation in data prefetching.	ISCA	2009	DBLP DOI BibTeX RDF	data prefetching
1	Yuejian Xie, Gabriel H. Loh	PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches.	ISCA	2009	DBLP DOI BibTeX RDF	cache, multi-core, sharing, contention, insertion, promotion
1	Xiaoyao Liang, Gu-Yeon Wei, David M. Brooks	ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.	ISCA	2008	DBLP DOI BibTeX RDF
1	Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan	Intra-disk Parallelism: An Idea Whose Time Has Come.	ISCA	2008	DBLP DOI BibTeX RDF
1	Derek Hower, Mark D. Hill	Rerun: Exploiting Episodes for Lightweight Memory Race Recording.	ISCA	2008	DBLP DOI BibTeX RDF
1	John Kim, William J. Dally, Steve Scott, Dennis Abts	Technology-Driven, Highly-Scalable Dragonfly Topology.	ISCA	2008	DBLP DOI BibTeX RDF
1	Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi	A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies.	ISCA	2008	DBLP DOI BibTeX RDF
1	Brandon Lucia, Joseph Devietti, Karin Strauss, Luis Ceze	Atom-Aid: Detecting and Surviving Atomicity Violations.	ISCA	2008	DBLP DOI BibTeX RDF
1	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri	iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures.	ISCA	2008	DBLP DOI BibTeX RDF
1	Franziska Roesner, Doug Burger, Stephen W. Keckler	Counting Dependence Predictors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Haibo Chen 0001, Xi Wu 0001, Liwei Yuan, Binyu Zang, Pen-Chung Yew, Frederic T. Chong	From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware.	ISCA	2008	DBLP DOI BibTeX RDF
1	Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, David A. Wood 0001	TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory.	ISCA	2008	DBLP DOI BibTeX RDF
1	Jae W. Lee, Man Cheuk Ng, Krste Asanovic	Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks.	ISCA	2008	DBLP DOI BibTeX RDF
1	Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn	Corona: System Implications of Emerging Nanophotonic Technology.	ISCA	2008	DBLP DOI BibTeX RDF
1	Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael P. Ryan, Evangelos Vlachos	Flexible Hardware Acceleration for Instruction-Grain Program Monitoring.	ISCA	2008	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Online Estimation of Architectural Vulnerability Factor for Soft Errors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd M. Austin	Polymorphic On-Chip Networks.	ISCA	2008	DBLP DOI BibTeX RDF
1	Lucas Kreger-Stickles, Mark Oskin	Microcoded Architectures for Ion-Tap Quantum Computers.	ISCA	2008	DBLP DOI BibTeX RDF
1	Taeho Kgil, David Roberts, Trevor N. Mudge	Improving NAND Flash Based Disk Caches.	ISCA	2008	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González 0001, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero	A Two-Level Load/Store Queue Based on Execution Locality.	ISCA	2008	DBLP DOI BibTeX RDF
1	Lee Baugh, Naveen Neelakantam, Craig B. Zilles	Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory.	ISCA	2008	DBLP DOI BibTeX RDF
1	Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz	Running a Quantum Circuit at the Speed of Data.	ISCA	2008	DBLP DOI BibTeX RDF
1	Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti	Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support.	ISCA	2008	DBLP DOI BibTeX RDF
1	Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie 0001, Narayanan Vijaykrishnan, Chita R. Das	MIRA: A Multi-layered On-Chip Interconnect Router Architecture.	ISCA	2008	DBLP DOI BibTeX RDF
1	Pablo Montesinos, Luis Ceze, Josep Torrellas	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently.	ISCA	2008	DBLP DOI BibTeX RDF
1	Sanjeev Kumar, Daehyun Kim 0001, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen	Atomic Vector Operations on Chip Multiprocessors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott	Flexible Decoupled Transactional Memory Support.	ISCA	2008	DBLP DOI BibTeX RDF
1	Nathan Clark, Amir Hormati, Scott A. Mahlke	VEAL: Virtualized Execution Accelerator for Loops.	ISCA	2008	DBLP DOI BibTeX RDF
1	Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana	Self-Optimizing Memory Controllers: A Reinforcement Learning Approach.	ISCA	2008	DBLP DOI BibTeX RDF
1	Radu Teodorescu, Josep Torrellas	Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors.	ISCA	2008	DBLP DOI BibTeX RDF
1		35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China	ISCA	2008	DBLP BibTeX RDF
1	Alex Shye, Berkin Özisikyilmaz, Arindam Mallik, Gokhan Memik, Peter A. Dinda, Robert P. Dick, Alok N. Choudhary	Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction.	ISCA	2008	DBLP DOI BibTeX RDF
1	Francis Tseng, Yale N. Patt	Achieving Out-of-Order Performance with Almost In-Order Complexity.	ISCA	2008	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	3D-Stacked Memory Architectures for Multi-core Processors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Kevin T. Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant D. Patel, Trevor N. Mudge, Steven K. Reinhardt	Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments.	ISCA	2008	DBLP DOI BibTeX RDF
1	Onur Mutlu, Thomas Moscibroda	Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems.	ISCA	2008	DBLP DOI BibTeX RDF
1	Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston	A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.	ISCA	2008	DBLP DOI BibTeX RDF
1	Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu	Trading off Cache Capacity for Reliability to Enable Low Voltage Operation.	ISCA	2008	DBLP DOI BibTeX RDF
1	Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matthew I. Frank	Fetch-Criticality Reduction through Control Independence.	ISCA	2008	DBLP DOI BibTeX RDF
1	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero	Software-Controlled Priority Characterization of POWER5 Processor.	ISCA	2008	DBLP DOI BibTeX RDF
1	Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Grasso Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun	An effective hybrid transactional memory system with strong isolation guarantees.	ISCA	2007	DBLP DOI BibTeX RDF	strong isolation, parallel programming, transactional memory, multi-core architectures
1	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith 0001	Configurable isolation: building high availability systems with commodity multi-core processors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, high availability, fault isolation
1	Weirong Zhu, Vugranam C. Sreedhar, Ziang Hu, Guang R. Gao	Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures.	ISCA	2007	DBLP DOI BibTeX RDF	SSB, fine-grain synchronization, many-core
1	Kyle J. Nesbit, James Laudon, James E. Smith 0001	Virtual private caches.	ISCA	2007	DBLP DOI BibTeX RDF	quality of service, chip multiprocessor, soft real-time, shared caches, performance isolation
1	Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer	Adaptive insertion policies for high performance caching.	ISCA	2007	DBLP DOI BibTeX RDF	set dueling, set sampling, thrashing, replacement
1	Abhishek Tiwari 0002, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
1	Colin Blundell, Joe Devietti, E. Christopher Lewis, Milo M. K. Martin	Making the fast case common and the uncommon case simple in unbounded transactional memory.	ISCA	2007	DBLP DOI BibTeX RDF	parallel programming, concurrency, transactions, transactional memory
1	Jayaram Bobba, Kevin E. Moore, Haris Volos 0001, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood 0001	Performance pathologies in hardware transactional memory.	ISCA	2007	DBLP DOI BibTeX RDF	performance, transactional memory, hardware, contention management, pathology
1	Tejas Karkhanis, James E. Smith 0001	Automated design of application specific superscalar processors: an analytical approach.	ISCA	2007	DBLP DOI BibTeX RDF	performance model, analytical model, design optimization, energy model, application specific processors
1	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang 0010	Thermal modeling and management of DRAM memory systems.	ISCA	2007	DBLP DOI BibTeX RDF	thermal management, thermal modeling, DRAM memories
1	Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha	Express virtual channels: towards the ideal interconnection fabric.	ISCA	2007	DBLP DOI BibTeX RDF	packet-switching, flow-control, router design
1	Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim 0001, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen	Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	parallelization, CMP, characterization, physical simulation
1	Dean M. Tullsen, Brad Calder (eds.)	34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA	ISCA	2007	DBLP DOI BibTeX RDF
1	Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam	Mechanisms for bounding vulnerabilities of processor structures.	ISCA	2007	DBLP DOI BibTeX RDF	redundant threading, microarchitecture, transient faults
1	David E. Shaw, Martin M. Deneroff, Ron O. Dror, Jeffrey Kuskin, Richard H. Larson, John K. Salmon, Cliff Young, Brannon Batson, Kevin J. Bowers, Jack C. Chao, Michael P. Eastwood, Joseph Gagliardo, J. P. Grossman, C. Richard Ho, Doug Ierardi, István Kolossváry, John L. Klepeis, Timothy Layman, Christine McLeavey, Mark A. Moraes, Rolf Mueller, Edward C. Priest, Yibing Shan, Jochen Spengler, Michael Theobald, Brian Towles, Stanley C. Wang	Anton, a special-purpose machine for molecular dynamics simulation.	ISCA	2007	DBLP DOI BibTeX RDF	biomolecular system simulation, computational drug design, special-purpose machine, bioinformatics, computational biology, molecular dynamics, protein folding, protein structure
1	Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler	Late-binding: enabling unordered load-store queues.	ISCA	2007	DBLP DOI BibTeX RDF	network flow control, memory disambiguation, late binding
1	Aashish Phansalkar, Ajay Joshi, Lizy Kurian John	Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite.	ISCA	2007	DBLP DOI BibTeX RDF	microprocessor performance counters, clustering, benchmark, SPEC
1	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto	Rotary router: an efficient architecture for CMP interconnection networks.	ISCA	2007	DBLP DOI BibTeX RDF	interconnection networks, router architecture, chip multi-processors
1	Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson	Aquacore: a programmable architecture for microfluidics.	ISCA	2007	DBLP DOI BibTeX RDF	fluidic, fluidic microarchitecture, programmable lab on a chip, microfluidics, instruction set
1	Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman	ParallAX: an architecture for real-time physics.	ISCA	2007	DBLP DOI BibTeX RDF	real-time physics, chip multiprocessor, physics based animation, stream processing, interactive entertainment, application specific processor
1	Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan 0003, Craig B. Zilles	Hardware atomicity for reliable software speculation.	ISCA	2007	DBLP DOI BibTeX RDF	Java, optimization, checkpoint, atomicity, speculation, isolation
1	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie 0001, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	A novel dimensionally-decomposed router for on-chip communication in 3D architectures.	ISCA	2007	DBLP DOI BibTeX RDF	3D architecture, 3D integration, network-on-chip (NoC)
1	Michael R. Marty, Mark D. Hill	Virtual hierarchies to support server consolidation.	ISCA	2007	DBLP DOI BibTeX RDF	virtual machines, partitioning, chip multiprocessors (CMPs), multicore, memory hierarchies, cache coherence, server consolidation
1	Eric Chi, Stephen A. Lyon, Margaret Martonosi	Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits.	ISCA	2007	DBLP DOI BibTeX RDF	architecture, quantum
1	Kristen R. Walcott, Greg Humphreys, Sudhanva Gurumurthi	Dynamic prediction of architectural vulnerability from microarchitectural state.	ISCA	2007	DBLP DOI BibTeX RDF	architecture vulnerability factor, redundant multithreading, performance, reliability, microarchitecture
1	Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau	Power model validation through thermal measurements.	ISCA	2007	DBLP DOI BibTeX RDF	power and thermal measurements
1	Michael Dalton, Hari Kannan, Christos Kozyrakis	Raksha: a flexible information flow architecture for software security.	ISCA	2007	DBLP DOI BibTeX RDF	semantic vulnerabilities, dynamic, software security
1	Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary	Transparent control independence (TCI).	ISCA	2007	DBLP DOI BibTeX RDF	control independence, selective re-execution, selective recovery, checkpoints, branch prediction, speculation
1	Xiaobo Fan, Wolf-Dietrich Weber, Luiz André Barroso	Power provisioning for a warehouse-sized computer.	ISCA	2007	DBLP DOI BibTeX RDF	power provisioning, energy efficiency, power modeling
1	Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Ricardo Bianchini	Limiting the power consumption of main memory.	ISCA	2007	DBLP DOI BibTeX RDF	power and energy management, performance, main memory
1	Zhenghong Wang, Ruby B. Lee	New cache designs for thwarting software cache-based side channel attacks.	ISCA	2007	DBLP DOI BibTeX RDF	security, cache, computer architecture, processor, timing attacks, side channel
1	Andrew D. Hilton, Amir Roth	Ginger: control independence using tag rewriting.	ISCA	2007	DBLP DOI BibTeX RDF	control independence, out-of-order renaming, selective re-dispatch, branch misprediction
1	Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel	Examining ACE analysis reliability estimates using fault-injection.	ISCA	2007	DBLP DOI BibTeX RDF	fault tolerance, microprocessors, soft errors, measurement techniques
1	Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn	VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.	ISCA	2007	DBLP DOI BibTeX RDF	devirtualization, indirect branch prediction, virtual functions
1	Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos	Mechanisms for store-wait-free multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	store buffer design, memory consistency models
1	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
1	John Kim, William J. Dally, Dennis Abts	Flattened butterfly: a cost-efficient topology for high-radix networks.	ISCA	2007	DBLP DOI BibTeX RDF	flattened butterfly, global adaptive routing, high-radix routers, interconnection networks, topology, cost model
1	Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin	Architectural implications of brick and mortar silicon manufacturing.	ISCA	2007	DBLP DOI BibTeX RDF	chip assembly, design re-use, interconnect design
1	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparing memory systems for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
1	Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black	Matrix scheduler reloaded.	ISCA	2007	DBLP DOI BibTeX RDF	picker, scheduler, microarchitecture, matrix, wakeup
1	Luis Ceze, James Tuck 0001, Pablo Montesinos, Josep Torrellas	BulkSC: bulk enforcement of sequential consistency.	ISCA	2007	DBLP DOI BibTeX RDF	bulk, chip multiprocessors, programmability, sequential consistency, memory consistency models
1	Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen	Carbon: architectural support for fine-grained parallelism on chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	loop and task parallelism, CMP, architectural support
1	Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng 0001, Jiang Jiang, Ying Zhang 0032	A 64-bit stream processor architecture for scientific applications.	ISCA	2007	DBLP DOI BibTeX RDF	architecture, compiler, high performance computing, program language, scientific application, stream processor
1	Hany E. Ramadan, Christopher J. Rossbach, Donald E. Porter, Owen S. Hofmann, Bhandari Aditya, Emmett Witchel	MetaTM//TxLinux: transactional memory for an operating system.	ISCA	2007	DBLP DOI BibTeX RDF	MetaTM, OS support, TxLinux, transactional memory
1	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	Core fusion: accommodating software diversity in chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, reconfigurable architectures, software diversity
1	Paul A. Karger	Performance and security lessons learned from virtualizing the alpha processor.	ISCA	2007	DBLP DOI BibTeX RDF	virtualizability, security, virtual machine monitors, hypervisors
1	Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott	An integrated hardware-software approach to flexible transactional memory.	ISCA	2007	DBLP DOI BibTeX RDF	RSTM, multiprocessors, transactional memory, cache coherence
1	Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos	Spatial Memory Streaming.	ISCA	2006	DBLP DOI BibTeX RDF
1		Message from the Program Chair.	ISCA	2006	DBLP DOI BibTeX RDF
1	Qing Yang 0001, Weijun Xiao, Jin Ren	TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time.	ISCA	2006	DBLP DOI BibTeX RDF

Publications at "ISCA"( http://dblp.L3S.de/Venues/ISCA )