Search results for "MPSoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Taewook Oh, Youngmin Yi, Soonhoi Ha	Communication Architecture Simulation on the Virtual Synchronization Framework.	SAMOS	2007	DBLP DOI BibTeX RDF
11	Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload.	ISVLSI	2007	DBLP DOI BibTeX RDF
11	Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant	Temperature aware task scheduling in MPSoCs.	DATE	2007	DBLP DOI BibTeX RDF
11	Paolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo	On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.	DSD	2007	DBLP DOI BibTeX RDF
11	Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod	Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere	Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.	FPL	2007	DBLP DOI BibTeX RDF
11	A. C. H. Ng, Jan-Willem Weijers, Miguel Glassee, Thomas Schuster, Bruno Bougard, Liesbet Van der Perre	ESL design and HW/SW co-verification of high-end software defined radio platforms.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	verification, emulation, SDR, hardware/software co-design, ESL
11	Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.	FCCM	2007	DBLP DOI BibTeX RDF
11	Junqing Sun, Gregory D. Peterson, Olaf O. Storaasli	Sparse Matrix-Vector Multiplication Design on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
11	Emiliano Dolif, Michele Lombardi 0001, Martino Ruggiero, Michela Milano, Luca Benini	Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip.	EMSOFT	2007	DBLP DOI BibTeX RDF	multimedia dataflow streaming, scheduling, allocation
11	Seongnam Kwon, Choonseung Lee, Soonhoi Ha	Data-Parallel Code Generation from Synchronous Dataflow Specification of Multimedia Applications.	ESTIMedia	2007	DBLP DOI BibTeX RDF
11	Slo-Li Chu	Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture.	LCPC	2007	DBLP DOI BibTeX RDF	Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
11	Olga Golubeva, Mirko Loghi, Massimo Poncino	On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	synchronization, multiprocessor, system-on-chip, energy
11	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	Communication Modelling of the Spidergon NoC with Virtual Channels.	ICPP	2007	DBLP DOI BibTeX RDF
11	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	An Analytical Performance Model for the Spidergon NoC.	AINA	2007	DBLP DOI BibTeX RDF
11	Walter H. Tibboel, Víctor Reyes, Martin Klompstra, Dennis Alders	System-Level Design Flow Based on a Functional Reference for HW and SW.	DAC	2007	DBLP DOI BibTeX RDF
11	Mahmut T. Kandemir	Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Banked memory systems, bank locality, compiler optimization, energy consumption, multiprocessor SoC
11	Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano	Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs.	CPAIOR	2006	DBLP DOI BibTeX RDF
11	Muhammad Farooq, Fabrice Muller, Michel Auguin	Contentions-conscious dynamic but deterministic scheduling of computational and communication tasks.	SAC	2006	DBLP DOI BibTeX RDF	deterministic scheduling, architecture, multiprocessor, SoC, RTOS
11	Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali	Supporting task migration in multi-processor systems-on-chip: a feasibility study.	DATE	2006	DBLP DOI BibTeX RDF
11	Andrea Alimonda, Andrea Acquaviva, Salvatore Carta, Alessandro Pisano	A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs.	DATE	2006	DBLP DOI BibTeX RDF
11	Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano	Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip.	DATE	2006	DBLP DOI BibTeX RDF
11	Ahmad Khonsari, Mohamed Ould-Khaoua, Abbas Nayebi, Hamid Sarbazi-Azad	The impacts of timing constraints on virtual channels multiplexing in interconnect networks.	IPCCC	2006	DBLP DOI BibTeX RDF
11	Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner	Topic 18: Embedded Parallel Systems.	Euro-Par	2006	DBLP DOI BibTeX RDF
11	Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami	REDEFIS: a system with a redefinable instruction set processor.	SBCCI	2006	DBLP DOI BibTeX RDF	ISA customization, dynamically reconfigurable processor, low power, SoC, high performance
11	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
11	Akash Kumar 0001, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha	Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip.	ESTIMedia	2006	DBLP DOI BibTeX RDF
11	Marcello Coppola	Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network.	IOLTS	2006	DBLP DOI BibTeX RDF
11	Fabio Wronski, Eduardo Wenzel Brião, Flávio Rech Wagner	Evaluating Energy-Aware Task Allocation Strategies for MPSOCS.	DIPES	2006	DBLP DOI BibTeX RDF	Simulation, Networks-on-Chip, Task Allocation, Multiprocessor SoCs, Energy Estimation
11	Grant Martin	Recent Developments in Configurable and Extensible Processors.	ASAP	2006	DBLP DOI BibTeX RDF
11	Michele Lombardi 0001, Michela Milano	Stochastic Allocation and Scheduling for Conditional Task Graphs in MPSoCs.	CP	2006	DBLP DOI BibTeX RDF
11	Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya	QOS Driven Network-on-Chip Design for Real Time Systems.	CCECE	2006	DBLP DOI BibTeX RDF
11	Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt	Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.	DAC	2006	DBLP DOI BibTeX RDF	customized memory hierarchy, multiprocessor data reuse analysis, scratch pad memory management
11	Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev	A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.	DAC	2006	DBLP DOI BibTeX RDF	hardware space exploration, embedded system design, multiprocessor system-on-chip, real-time analysis, electrocardiogram algorithms
11	Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli	xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.	DATE	2005	DBLP DOI BibTeX RDF
11	Srinivasan Murali, Giovanni De Micheli	An Application-Specific Design Methodology for STbus Crossbar Generation.	DATE	2005	DBLP DOI BibTeX RDF
11	Mahmut T. Kandemir, Guilin Chen	Locality-Aware Process Scheduling for Embedded MPSoCs.	DATE	2005	DBLP DOI BibTeX RDF
11	Víctor Reyes, Tomás Bautista, Gustavo Marrero Callicó, Antonio Núñez, Wido Kruijtzer	A multicast inter-task communication protocol for embedded multiprocessor systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	multiprocessor design, platform interface, task transaction level, parallel programming model
11	Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano	Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation.	CP	2005	DBLP DOI BibTeX RDF
11	Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino	Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, multiprocessor, system-on-chip, cache coherence
11	Mahmut T. Kandemir	Exploiting Memory Bank Locality in Multiprocessor SoC Architectures.	IPDPS	2004	DBLP DOI BibTeX RDF
11	Jaehwan Lee 0002, Vincent John Mooney III	A novel deadlock avoidance algorithm and its hardware implementation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	deadlock avoidance hardware IP design
11	Pieter van der Wolf, Erwin A. de Kock, Tomas Henriksson, Wido Kruijtzer, Gerben Essink	Design and programming of embedded multiprocessors: an interface-centric approach.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	multiprocessor mapping, platform interface, system design method, task-level interface, code transformation, media processing
11	Ferid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya	An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
11	Mirko Loghi, Massimo Poncino, Luca Benini	Cycle-accurate power analysis for multiprocessor systems-on-a-chip.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, multiprocessor, system-on-chip
11	Sudarshan Banerjee, Nikil D. Dutt	FIFO power optimization for on-chip networks.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	wide flits, low power design, shared memory, switches, FIFO, on-chip networks
11	John L. Gustafson	Reevaluating Amdahl's Law.	Commun. ACM	1988	DBLP DOI BibTeX RDF