Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Jayanand Asok Kumar, Shobha Vasudevan |
Variation-Conscious Formal Timing Verification in RTL. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski |
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg |
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. |
ISCA |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara |
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. |
IEICE Trans. Inf. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak |
On Reducing Scan Shift Activity at RTL. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara |
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences. |
J. Electron. Test. |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara |
A synthesis method to propagate false path information from RTL to gate level. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Hendra Setiawan, Hiroshi Ochi |
An optimum RTL design of time domain auto-correlation architecture for WiMAX OFDMA and 3GPP LTE cooperative system. |
PIMRC |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Bryan A. Brady, Randal E. Bryant, Sanjit A. Seshia, John W. O'Leary |
ATLAS: Automatic Term-level abstraction of RTL designs. |
MEMOCODE |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Volodymyr Obrizan |
A method for automatic generation of an RTL-interface from a C++ description. |
EWDTS |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Nadereh Hatami, Marco Indaco, Paolo Prinetto, Gabriele Tiotto |
Communication interface synthesis from TLM 2.0 to RTL. |
EWDTS |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Hong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dobbyn, Sy-Yen Kuo |
Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai |
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
15 | John Sanguinetti, Eugene Zhang |
The relationship of code coverage metrics on high-level and RTL code. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Martin Schweikert, Hans Eveking |
Verwendung von UML Sequenzdiagrammen zur Spezifikation und Generierung von RTL Eigenschaftssätzen. |
MBMV |
2010 |
DBLP BibTeX RDF |
|
15 | Hirofumi Kawauchi, Masanori Tsuzuki, Ittetsu Taniguchi, Masahiro Fukui |
An accurate RTL power estimation considering power library unevenness. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto |
Design metrics for RTL level estimation of delay variability due to intradie (random) variations. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Mainak Banga, Michael S. Hsiao |
Trusted RTL: Trojan Detection Methodology in Pre-silicon Designs. |
HOST |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Abhay Singh, Milan Shetty, Srivaths Ravi 0001, Ravindra Nibandhe |
Methodology for early and accurate test power estimation at RTL. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
Constrained ATPG for functional RTL circuits using F-Scan. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Ho Fai Ko, Nicola Nicolici |
Automated trace signals selection using the RTL descriptions. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara |
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
path mapping, false path, functional equivalence, high level testing |
15 | Sven Rosinger, Domenik Helms, Wolfgang Nebel |
RTL power modeling and estimation of sleep transistor based power gating. |
J. Embed. Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty |
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui |
An Efficient Algorithm for RTL Power Macro-Modeling and Library Building. |
IEICE Trans. Electron. |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Sara Vinco |
Correct-by-construction generation of device drivers based on RTL testbenches. |
DATE |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley |
Solver technology for system-level to RTL equivalence checking. |
DATE |
2009 |
DBLP DOI BibTeX RDF |
|
15 | George Economakos, Sotirios Xydis |
Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Abel G. Silva-Filho, Sidney M. L. Lima, F. C. L. Cox |
Low Power RTL Exploration Mechanism Based on the Cache Parameters. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Exploration Mechanism, NIOSII, FPGA, Embedded Systems, SoC, Low Power Design, Cache Memory |
15 | Lingyi Liu, Shobha Vasudevan |
STAR: Generating input vectors for design validation by static analysis of RTL. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara |
RTL DFT techniques to enhance defect coverage for functional test sequences. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Saraju P. Mohanty, Bijaya K. Panigrahi |
ILP based Leakage Optimization during Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective. |
NaBIC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Fabio Campi, Ralf König 0001, Michael Dreschmann, M. Neukirchner, Damien Picard, M. Jüttner, Eberhard Schüler, Antonio Deledda, Davide Rossi, Alberto Pasini, Michael Hübner 0001, Jürgen Becker 0001, Roberto Guerrieri |
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip. |
SoC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu |
Sequential equivalence checking between system level and RTL descriptions. |
Des. Autom. Embed. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Aric D. Blumer, Cameron D. Patterson |
Exploiting Process Locality of Reference in RTL Simulation Acceleration. |
EURASIP J. Embed. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Wei Huang 0004, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, Mircea R. Stan |
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Guilherme Montez Guindani, Cezar Reinbrecht, Thiago Raupp da Rosa, Ney Calazans, Fernando Gehm Moraes |
NoC Power Estimation at the RTL Abstraction Level. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Tom English, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens |
HotSpot: Visualizing dynamic power consumption in RTL designs. |
EWDTS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
RTL-TLM equivalence checking based on simulation. |
EWDTS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara |
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. |
ATS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jeongwoo Park, Bongchun Lee, Kyu-sam Lim, Jeong Hun Kim, Suki Kim, Kwang-Hyun Baek |
Co-simulation of SystemC TLM with RTL HDL for surveillance camera system verification. |
ICECS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jinhyun Cho, Soonwoo Choi, Soo-Ik Chae |
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow. |
FDL |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Assertion Synthesis, Assertion Unification, Online Testing |
15 | Saeed Mirzaeian, Feijun (Frank) Zheng, Kwang-Ting (Tim) Cheng |
RTL Error Diagnosis Using a Word-Level SAT-Solver. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Giuseppe Falconeri, Walid Naifer, Nizar Romdhane |
Common Reusable Verification Environment for BCA and RTL Models |
CoRR |
2007 |
DBLP BibTeX RDF |
|
15 | Jarrod A. Roy, David A. Papa, Igor L. Markov |
Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability. |
Modern Circuit Placement |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yang Guo 0003, WanXia Qu, Tun Li, Sikun Li |
Coverage Driven Test Generation Framework for RTL Functional Verification. |
CAD/Graphics |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Sven Rosinger, Domenik Helms, Wolfgang Nebel |
RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Daniel Kroening, Natasha Sharygina |
Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Alan Naumann |
Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore's law? |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Eric Cheung, Xi Chen 0024, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh |
Bridging RTL and gate: correlating different levels of abstraction for design debugging. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov |
Automatic error diagnosis and correction for RTL designs. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Mingsong Chen, Prabhat Mishra 0001, Dhrubajyoti Kalita |
Towards RTL test generation from SystemC TLM specifications. |
HLDVT |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao |
EHSAT Modeling from Algorithm Description for RTL Model Checking. |
ATS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yu Huang 0005, Nilanjan Mukherjee 0001, Wu-Tung Cheng, Greg Aldrich |
A RTL Testability Analyzer Based on Logical Virtual Prototyping. |
ATS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara |
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. |
ATS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Rainer Dorsch, Jürgen Ruf |
Transaction Modeling and RTL Simulation Analysis. |
MBMV |
2007 |
DBLP BibTeX RDF |
|
15 | Xianyang Jiang, Xiaomin Li, Yue Tian, Kai Wang |
NICFlex: A Functional Verification Accelerator for An RTL NIC Design. |
FPT |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Ping-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang |
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. |
ISSCC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Jian Kang, Sharad C. Seth, Vijay Gangaram |
Efficient RTL Coverage Metric for Functional Test Selection. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Atsushi Kasuya, Tesh Tesfaye |
Verification Methodologies in a TLM-to-RTL Design Flow. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu |
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. |
J. Inf. Sci. Eng. |
2006 |
DBLP BibTeX RDF |
|
15 | Tomokazu Yoneda, Hideo Fujiwara |
Design for consecutive transparency method of RTL circuits. |
Syst. Comput. Jpn. |
2006 |
DBLP DOI BibTeX RDF |
|
15 | José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira 0001 |
Probabilistic Testability Analysis and DFT Methods at RTL. |
DDECS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Chao-Lieh Chen, Yao-De Huang |
Distributed Fuzzy Controller for the IEEE 802.11e QoS and Its RTL Fast Prototyping. |
FUZZ-IEEE |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Youngsoo Kim, William W. Edmonson |
H.264 Video Decoder Design: Beyond RTL Design Implementation. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Cacho Teixeira |
DFT and Probabilistic Testability Analysis at RTL. |
HLDVT |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Nitin Yogi, Vishwani D. Agrawal |
Spectral RTL Test Generation for Gate-Level Stuck-at Faults. |
ATS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Alan Hu |
High-Level vs. RTL Combinational Equivalence: An Introduction. |
ICCD |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Ho Fai Ko, Nicola Nicolici |
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. |
ICCD |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Shiv Tasker, Rishiyur S. Nikhil |
Beyond RTL: Advanced Digital System Design. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Karina R. G. da Silva, Elmar U. K. Melcher, Isaac Maia, Henrique do N. Cunha |
A methodology aimed at better integration of functional verification and RTL design. |
Des. Autom. Embed. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Marco Bozzano, Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Ziyad Hanna, Zurab Khasidashvili, Amit Palti, Roberto Sebastiani |
Encoding RTL Constructs for MathSAT: a Preliminary Report. |
PDPAR@CAV |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara |
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. |
IEICE Trans. Inf. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Nacer-Eddine Zergainoh, Ludovic Tambour, Henri Michel, Ahmed Amine Jerraya |
Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation. |
Tech. Sci. Informatiques |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Ridha Djemal, Ayoub Dhouib, Samuel Dellacherie, Rached Tourki |
A novel formal verification approach for RTL hardware IP cores. |
Comput. Stand. Interfaces |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Nikolaos D. Liveris, Hai Zhou 0001, Prithviraj Banerjee |
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Tun Li, Yang Guo 0003, Sikun Li, GongJie Liu |
Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming. |
ATVA |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Tun Li, Yang Guo 0003, Sikun Li, Dan Zhu |
Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions. |
MICAI |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Peter Jamieson, Jonathan Rose |
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. |
FPL |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Felipe Machado, Teresa Riesgo, Yago Torroja |
Switching activity propagation of VHDL-RTL combinational designs through an automated tool. |
ICECS |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Alfred Kölbl, Yuan Lu, Anmol Mathur |
Embedded tutorial: formal equivalence checking between system-level models and RTL. |
ICCAD |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer |
RTL SAT simplification by Boolean and interval arithmetic reasoning. |
ICCAD |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel |
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. |
Evolvable Hardware |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jiong Luo, Lin Zhong 0001, Yunsi Fei, Niraj K. Jha |
Register binding-based RTL power management for control-flow intensive designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Dwight D. Hill, Andrew B. Kahng |
Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice. |
IEEE Des. Test Comput. |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Rishiyur S. Nikhil |
Bluespec System Verilog: efficient, correct RTL from high level specifications. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Andrea Del Re, Alberto Nannarelli, Marco Re |
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Prasenjit Basu, Sayantan Das 0001, Pallab Dasgupta, P. P. Chakrabarti 0001, Chunduri Rama Mohan, Limor Fix |
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl |
RTL Processor Synthesis for Architecture Exploration and Implementation. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Daniel Mika, Josef Strnadel, Zdenek Kotásek |
The Identification of registers in RTL Structures for the Test Application. |
ISoLA (Preliminary proceedings) |
2004 |
DBLP BibTeX RDF |
|
15 | William N. N. Hung, Naren Narasimhan |
Reference model based RTL verification: an integrated approach. |
HLDVT |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Masahiro Fujita |
On equivalence checking between behavioral and RTL descriptions. |
HLDVT |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Ho Fai Ko, Nicola Nicolici |
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
High-level DFT, Delay-fault testing |
15 | Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera |
RTL/ISS co-modeling methodology for embedded processor using SystemC. |
ISCAS (5) |
2004 |
DBLP BibTeX RDF |
|
15 | Xin Wang, Tapani Ahonen, Jari Nurmi |
A synthesizable RTL design of asynchronous FIFO. |
SoC |
2004 |
DBLP DOI BibTeX RDF |
|