Search results for "SPICE"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Uwe Zillmann, Frank Herzel	An improved SPICE model for high-frequency noise of BJTs and HBTs.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
16	A. Srivastava, S. R. Palavali	Integration of SPICE with TEK LV500 ASIC Design Verification System.	VLSI Design	1996	DBLP DOI BibTeX RDF
16	David H. Kitson	Relating the SPICE framework and SEI approach to software process assessment.	Softw. Qual. J.	1996	DBLP DOI BibTeX RDF
16	Khaled El Emam, Dennis R. Goldenson	An Empirical Evaluation of the Prospective International SPICE Standard.	Softw. Process. Improv. Pract.	1996	DBLP DOI BibTeX RDF
16	Takeshige Miyoshi	Early Experience with Software Process Assessment using SPICE Framework at Software Research Associates, Inc.	Softw. Process. Improv. Pract.	1996	DBLP DOI BibTeX RDF
16	Khaled El Emam, Lionel C. Briand, Robert Smith	Assessor agreement in rating SPICE processes.	Softw. Process. Improv. Pract.	1996	DBLP DOI BibTeX RDF
16	Jean-Martin Simon	SPICE: Overview for software process improvement.	J. Syst. Archit.	1996	DBLP DOI BibTeX RDF
16	Franc Mihalic, Karel Jezernik, Klaus Krischan, Manfred Rentmeister	IGBT SPICE model.	IEEE Trans. Ind. Electron.	1995	DBLP DOI BibTeX RDF
16	Edwin X. Li, Norman Scheinberg, Daniel Stofman, William Tompkins	An independently matched parameter SPICE model for GaAs MESFET's.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
16	Terence P. Rout	SPICE: A Framework for Software Process Assessment.	Softw. Process. Improv. Pract.	1995	DBLP BibTeX RDF
16	Jay D. Beams	Adding spice to software development: a software development approach designed for rapidly changing environments.	SAC	1995	DBLP DOI BibTeX RDF	prototyping, requirements, development
16	Antonio Coletta	The SPICE Project: An International Standard for Software Process Assessment, Improvement and Capability Determination.	Objective Software Quality	1995	DBLP DOI BibTeX RDF
16	Gordon W. Roberts	Calculating Distortion Levels in Sampled-Data Circuits Using SPICE.	ISCAS	1995	DBLP DOI BibTeX RDF
16	Johan Scholliers, Timo Yli-Pietilä	A SPICE-Based Library for Mechatronic Systems.	ISCAS	1995	DBLP DOI BibTeX RDF
16	Jaap Hoekstra, Petra Mantel	Aspects of Spatiotemporal Learning in Artificial Neural Networks: Modeling Synaptic Membrane Currents Using SPICE Simulations.	SNN Symposium on Neural Networks	1995	DBLP DOI BibTeX RDF
16	Sudhir M. Gowda, Bing J. Sheu	BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
16	Marco Bove, Giuseppe Massobrio, Sergio Martinoia, Massimo Grattarola	Realistic simulations of neurons by means of an ad hoc modified version of SPICE.	Biol. Cybern.	1994	DBLP DOI BibTeX RDF
16	Hans Georg Brachtendorf, Rainer Laur	Modeling of Frequency-dependent Hysteresis with SPICE.	ISCAS	1994	DBLP DOI BibTeX RDF
16	Kazuki Yasumatsu, Norihisa Doi	SPiCE: A System for Translating Smalltalk Programs into a C Environment.	ICCL	1994	DBLP DOI BibTeX RDF
16	Qingjian Yu, Omar Wing	A SPICE Model of RLGC Transmission Line with Error Control.	VLSI Design	1994	DBLP DOI BibTeX RDF
16	Jianping Xu, Manfred Grötzbach	Time-domain analysis of half-wave zero-current switch quasi-resonant converters by using SPICE.	IEEE Trans. Ind. Electron.	1993	DBLP DOI BibTeX RDF
16	David T. Zweidinger, Sang-Gug Lee 0001, Robert M. Fox	Compact modeling of BJT self-heating in SPICE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
16	Dario D'Amore, William Fornaciari	A spice-based approach to steady state circuit analysis.	Int. J. Circuit Theory Appl.	1993	DBLP DOI BibTeX RDF
16	A. Dorling	SPICE: Software process improvement and capability dEtermination.	Inf. Softw. Technol.	1993	DBLP DOI BibTeX RDF
16	E. Schurack, Thomas Latzel, Alfons Gottwald	SPICE-simulation of Nonlinear Effects in Filed-Effect-Transistors Caused by Thermal Power Feedback.	ISCAS	1993	DBLP BibTeX RDF
16	José I. Alonso, Félix Pérez	SPICE implementation of nonuniform frequency-dependent transmission lines.	ISCAS	1993	DBLP BibTeX RDF
16	Scott Diamond, Bo Janko	Extraction of Coupled SPICE Models for Packages and Interconnects.	ITC	1993	DBLP DOI BibTeX RDF
16	Tai-Yu Chou, Jay Cosentino, Zoltan J. Cendes	High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods.	DAC	1993	DBLP DOI BibTeX RDF
16	Hans Georg Brachtendorf, Rainer Laur	A SPICE Macromodel for Nonlinear Magnetic Cores with Hysteresis.	EUROSIM	1992	DBLP BibTeX RDF
16	Hong June Park, Ping Keung Ko, Chenming Hu	A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
16	Hansruedi Heeb, Albert E. Ruehli	Retarded Models for PC Board Interconnects - Or How the Speed of Light Affects your SPICE Circuit Simulation.	ICCAD	1991	DBLP DOI BibTeX RDF
16	Karl Wolters, O. Behnke	Hardware-Modeler für Gleichspannungsanalyse mit dem Simulator Spice.	ASIM	1990	DBLP BibTeX RDF
16	Rao Prakash Pokala, Dileep A. Divekar	Thermal analysis in SPICE.	ICCAD	1989	DBLP DOI BibTeX RDF
16	S. L. Wong, C. André T. Salama	Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1987	DBLP DOI BibTeX RDF
16	Surya Veeraraghavan, Jerry G. Fossum, William R. Eisenstadt	SPICE Simulation of SOI MOSFET Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1986	DBLP DOI BibTeX RDF
16	Gregory J. Fisher, J. Alvin Connelly	Modeling Time-Dependent Elements for SPICE Transient Analyses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1986	DBLP DOI BibTeX RDF
16	Roger B. Dannenberg, Peter G. Hibbard	A Butler Process for Resource Sharing on Spice Machines.	ACM Trans. Inf. Syst.	1985	DBLP DOI BibTeX RDF
16	Di Ma	A Physical and SPICE-Compatible Model for the MOS Depletion Device.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1985	DBLP DOI BibTeX RDF
16	Peter Jedele, Haybatolah Khakzar	Analyse nichtlinearer frequenzabhängiger Übertragungssysteme mit Volterra-Reihen und dem Simulationsprogramm SPICE.	Simulationstechnik	1985	DBLP DOI BibTeX RDF
16	A. Stürmer	Meß- und Auswerte-System (MAUS) und dessen Einsatz zur Bestimmung von Modellparametern zur Simulation mit dem Netzwerkanalyseprogramm SPICE.	Simulationstechnik	1984	DBLP DOI BibTeX RDF
16	Morris Balamut, Ed Kinnen, Rosanne Wyleczuk	Spice Rack.	Integr.	1983	DBLP DOI BibTeX RDF
16	You-Pang Wei	Large-Scale Circuit Simulation (Vlsi, Spice, Premos, Analysis, Sequencing, Nonlinear, Iteration, Gauss-Seidel)		1983	RDF
16	Ping Yang 0001, Pallab K. Chatterjee	SPICE Modeling for Small Geometry MOSFET Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1982	DBLP DOI BibTeX RDF
15	Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li 0001	Accurate clock mesh sizing via sequential quadraticprogramming.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, sequential quadratic programming
15	Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma	DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing.	J. Glob. Optim.	2009	DBLP DOI BibTeX RDF	Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution
15	Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001	Closed-loop modeling of power and temperature profiles of FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	sub-threshold leakage, dynamic power
15	He Peng, Chung-Kuan Cheng	Parallel transistor level circuit simulation using domain decomposition methods.	ASP-DAC	2009	DBLP DOI BibTeX RDF
15	Rajesh Garg, Sunil P. Khatri	Efficient analytical determination of the SEU-induced pulse shape.	ASP-DAC	2009	DBLP DOI BibTeX RDF
15	Renatas Jakushokas, Eby G. Friedman	Simultaneous shield and repeater insertion.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay, interconnects, noise, power, area
15	Debasish Das, William Scott, Shahin Nazarian, Hai Zhou 0001	An efficient current-based logic cell model for crosstalk delay analysis.	ISQED	2009	DBLP DOI BibTeX RDF
15	Bo Hu, C.-J. Richard Shi	Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
15	Amit Goel, Sarma B. K. Vrudhula	Current source based standard cell model for accurate signal integrity and timing analysis.	DATE	2008	DBLP DOI BibTeX RDF
15	Bao Liu 0001	Signal Probability Based Statistical Timing Analysis.	DATE	2008	DBLP DOI BibTeX RDF
15	Yuichi Tanji, Takayuki Watanabe, Hideki Asai	Generating stable and sparse reluctance/inductance matrix under insufficient conditions.	ASP-DAC	2008	DBLP DOI BibTeX RDF
15	Ludek Zaloudek, Lukás Sekanina	Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator.	ICES	2008	DBLP DOI BibTeX RDF
15	Victoria Wang, Dejan Markovic	Linear analysis of random process variability.	ICCAD	2008	DBLP DOI BibTeX RDF
15	Dimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos	A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions.	ICCD	2008	DBLP DOI BibTeX RDF
15	Charles Thangaraj, Tom Chen 0001	Design target exploration for meeting time-to-market using pareto analysis.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Massimo Alioto, Massimo Poli, Gaetano Palumbo	Explicit energy evaluation in RLC tree circuits with ramp inputs.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Likun Xia, Ian M. Bell, Antony J. Wilkinson	A novel approach for automated model generation.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation Aware Spline Center and Range Modeling for Analog Circuit Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Center and Range, Process Variation, Analog, Spline
15	Rouwaida Kanj, Zhuo Li 0001, Rajiv V. Joshi, Frank Liu 0001, Sani R. Nassif	A Root-Finding Method for Assessing SRAM Stability.	ISQED	2008	DBLP DOI BibTeX RDF	stability, memory, yield, sram, roots
15	Vinay Jain, Payman Zarkesh-Ha	Analytical Noise-Rejection Model Based on Short Channel MOSFET.	ISQED	2008	DBLP DOI BibTeX RDF
15	Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind	Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Amit Goel, Sarma B. K. Vrudhula	Statistical waveform and current source based standard cell models for accurate timing analysis.	DAC	2008	DBLP DOI BibTeX RDF	statistical waveform models, process variations, timing analysis
15	Peng Li 0001, Zhuo Feng, Emrah Acar	Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
15	Saurabh K. Tiwary, Joel R. Phillips	WAVSTAN: waveform based variational static timing analysis.	DATE	2007	DBLP DOI BibTeX RDF
15	Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen	A technique for selecting CMOS transistor orders.	ICCD	2007	DBLP DOI BibTeX RDF
15	Tsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, Kwang-Ting Cheng	Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver.	DAC	2007	DBLP DOI BibTeX RDF
15	Ashesh Rastogi, Wei Chen, Sandip Kundu	On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.	DAC	2007	DBLP DOI BibTeX RDF
15	Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	SWAN: high-level simulation methodology for digital substrate noise generation.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
15	Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta	Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Zhao Li, C.-J. Richard Shi	A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi	Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu	Time-domain analysis methodology for large-scale RLC circuits and its applications.	Sci. China Ser. F Inf. Sci.	2006	DBLP DOI BibTeX RDF	RLC circuits, analog circuit analysis, P/G networks, algorithm complexity, time-domain analysis
15	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Soft delay error analysis in logic circuits.	DATE	2006	DBLP DOI BibTeX RDF
15	Kiyotaka Yamamura, Wataru Kuroki	An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Xiaolue Lai, Jaijeet S. Roychowdhury	Macromodelling oscillators using Krylov-subspace methods.	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Douglas R. Hickey, Philip A. Wilsey, Robert J. Hoekstra, Eric R. Keiter, Scott A. Hutchinson, Thomas V. Russo	Mixed-Signal Simulation with the Simbus Backplane.	Annual Simulation Symposium	2006	DBLP DOI BibTeX RDF
15	Saurabh K. Tiwary, Rob A. Rutenbar	Faster, parametric trajectory-based macromodels via localized linear reductions.	ICCAD	2006	DBLP DOI BibTeX RDF
15	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Statistical crosstalk aggressor alignment aware interconnect delay calculation.	SLIP	2006	DBLP DOI BibTeX RDF
15	Massimo Alioto, Gaetano Palumbo, Massimo Poli	Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Andrei Vladimirescu, Radu Zlatanovici, Paul G. A. Jespers	Analog circuit synthesis using standard EDA tools.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Peter Wright, Minghui Fan	A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit.	ISQED	2006	DBLP DOI BibTeX RDF
15	Taeyong Je, Yungseon Eo	Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching.	ISQED	2006	DBLP DOI BibTeX RDF
15	Hidetomo Nabeshima, Reiko Miyagawa, Yuki Suzuki, Koji Iwanuma	Rapid Synthesis of Domain-Specific Web Search Engines Based on Semi-Automatic Training-Example Generation.	Web Intelligence	2006	DBLP DOI BibTeX RDF
15	Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin	Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.	VLSI Design	2006	DBLP DOI BibTeX RDF
15	Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury	ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong	IR Drop and Ground Bounce Awareness Timing Model.	ISVLSI	2005	DBLP DOI BibTeX RDF
15	Zhengtao Yu 0002, Xun Liu	Power Analysis of Rotary Clock.	ISVLSI	2005	DBLP DOI BibTeX RDF
15	Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor	Framework for Fault Analysis and Test Generation in DRAMs.	DATE	2005	DBLP DOI BibTeX RDF
15	Zhao Li, C.-J. Richard Shi	An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.	DATE	2005	DBLP DOI BibTeX RDF
15	Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury	Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Michael Walter Payton, Fat Duen Ho	A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation PART-I MOSFETs and CMOS inverters.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
15	Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang	On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Michael Walter Payton, Fat Duen Ho	A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Ki-Won Song, Kyung-Whan Lee	Design of Opportunity Tree Framework for Effective Process Improvement based on Quantitative Project Performance.	SERA	2005	DBLP DOI BibTeX RDF
15	Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan	Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
15	Kartik Mohanram	Closed-Form Simulation and Robustness Models for SEU-Tolerant Design.	VTS	2005	DBLP DOI BibTeX RDF
15	Claudia Kretzschmar, Torsten Bitterlich, Dietmar Müller 0001	A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses.	PATMOS	2004	DBLP DOI BibTeX RDF