Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Uwe Zillmann, Frank Herzel |
An improved SPICE model for high-frequency noise of BJTs and HBTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(9), pp. 1344-1346, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | A. Srivastava, S. R. Palavali |
Integration of SPICE with TEK LV500 ASIC Design Verification System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 4(1), pp. 69-74, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | David H. Kitson |
Relating the SPICE framework and SEI approach to software process assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 5(3), pp. 145-156, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Khaled El Emam, Dennis R. Goldenson |
An Empirical Evaluation of the Prospective International SPICE Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Process. Improv. Pract. ![In: Softw. Process. Improv. Pract. 2(2), pp. 123-148, June 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Takeshige Miyoshi |
Early Experience with Software Process Assessment using SPICE Framework at Software Research Associates, Inc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Process. Improv. Pract. ![In: Softw. Process. Improv. Pract. 2(3), pp. 211-235, September 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Khaled El Emam, Lionel C. Briand, Robert Smith |
Assessor agreement in rating SPICE processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Process. Improv. Pract. ![In: Softw. Process. Improv. Pract. 2(4), pp. 291-306, December 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Jean-Martin Simon |
SPICE: Overview for software process improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 42(8), pp. 633-641, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Franc Mihalic, Karel Jezernik, Klaus Krischan, Manfred Rentmeister |
IGBT SPICE model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 42(1), pp. 98-105, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Edwin X. Li, Norman Scheinberg, Daniel Stofman, William Tompkins |
An independently matched parameter SPICE model for GaAs MESFET's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(8), pp. 872-880, August 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Terence P. Rout |
SPICE: A Framework for Software Process Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Process. Improv. Pract. ![In: Softw. Process. Improv. Pract. 1(1), pp. 57-66, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
16 | Jay D. Beams |
Adding spice to software development: a software development approach designed for rapidly changing environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1995 ACM symposium on applied computing, SAC'95, Nashville, TN, USA, February 26-28, 1995, pp. 384-389, 1995, ACM, 0-89791-658-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
prototyping, requirements, development |
16 | Antonio Coletta |
The SPICE Project: An International Standard for Software Process Assessment, Improvement and Capability Determination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Objective Software Quality ![In: Objective Software Quality: Second Symposium on Software Quality Techniques and Acquisition Criteria, Florence, Italy, May 29-31, 1995, Proceedings, pp. 49-63, 1995, Springer, 3-540-59449-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Gordon W. Roberts |
Calculating Distortion Levels in Sampled-Data Circuits Using SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 2059-2062, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Johan Scholliers, Timo Yli-Pietilä |
A SPICE-Based Library for Mechatronic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 668-671, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Jaap Hoekstra, Petra Mantel |
Aspects of Spatiotemporal Learning in Artificial Neural Networks: Modeling Synaptic Membrane Currents Using SPICE Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SNN Symposium on Neural Networks ![In: Neural Networks: Artificial Intelligence and Industrial Applications - Proceedings of the Third Annual SNN Symposium on Neural Networks, Nijmegen, The Netherlands, September 14-15, 1995, pp. 47-50, 1995, Springer, 978-3-540-19992-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Sudhir M. Gowda, Bing J. Sheu |
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1166-1170, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Marco Bove, Giuseppe Massobrio, Sergio Martinoia, Massimo Grattarola |
Realistic simulations of neurons by means of an ad hoc modified version of SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biol. Cybern. ![In: Biol. Cybern. 71(2), pp. 137-145, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Hans Georg Brachtendorf, Rainer Laur |
Modeling of Frequency-dependent Hysteresis with SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 343-346, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Kazuki Yasumatsu, Norihisa Doi |
SPiCE: A System for Translating Smalltalk Programs into a C Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCL ![In: Proceedings of the IEEE Computer Society 1994 International Conference on Computer Languages, May 16-19, 1994, Toulouse, France, pp. 113-123, 1994, IEEE Computer Society, 0-8186-5640-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Qingjian Yu, Omar Wing |
A SPICE Model of RLGC Transmission Line with Error Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 57-60, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Jianping Xu, Manfred Grötzbach |
Time-domain analysis of half-wave zero-current switch quasi-resonant converters by using SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 40(6), pp. 577-579, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | David T. Zweidinger, Sang-Gug Lee 0001, Robert M. Fox |
Compact modeling of BJT self-heating in SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9), pp. 1368-1375, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Dario D'Amore, William Fornaciari |
A spice-based approach to steady state circuit analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 21(5), pp. 437-442, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | A. Dorling |
SPICE: Software process improvement and capability dEtermination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Softw. Technol. ![In: Inf. Softw. Technol. 35(6-7), pp. 404-406, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | E. Schurack, Thomas Latzel, Alfons Gottwald |
SPICE-simulation of Nonlinear Effects in Filed-Effect-Transistors Caused by Thermal Power Feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 1116-1119, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
16 | José I. Alonso, Félix Pérez |
SPICE implementation of nonuniform frequency-dependent transmission lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 2299-2302, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
16 | Scott Diamond, Bo Janko |
Extraction of Coupled SPICE Models for Packages and Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 436-445, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Tai-Yu Chou, Jay Cosentino, Zoltan J. Cendes |
High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 684-690, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Hans Georg Brachtendorf, Rainer Laur |
A SPICE Macromodel for Nonlinear Magnetic Cores with Hysteresis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROSIM ![In: Eurosim 1992, Simulation Congress, Proceedings of the 1992 EUROSIM Conference, Capri, Italy, September 28 - October 4, 1992., pp. 429-434, 1992, Elsevier, 0-444-89331-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
16 | Hong June Park, Ping Keung Ko, Chenming Hu |
A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 629-642, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Hansruedi Heeb, Albert E. Ruehli |
Retarded Models for PC Board Interconnects - Or How the Speed of Light Affects your SPICE Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 70-73, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Karl Wolters, O. Behnke |
Hardware-Modeler für Gleichspannungsanalyse mit dem Simulator Spice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIM ![In: 6. Symposium Simulationstechnik: Fortschritte in der Simulationstechnik, ASIM 1990, Vienna, Austria, September, 1990., pp. 566-570, 1990, Vieweg, 3-528-06401-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
16 | Rao Prakash Pokala, Dileep A. Divekar |
Thermal analysis in SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers, pp. 256-259, 1989, IEEE Computer Society, 0-8186-1986-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
16 | S. L. Wong, C. André T. Salama |
Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(4), pp. 586-591, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
16 | Surya Veeraraghavan, Jerry G. Fossum, William R. Eisenstadt |
SPICE Simulation of SOI MOSFET Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4), pp. 653-658, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
16 | Gregory J. Fisher, J. Alvin Connelly |
Modeling Time-Dependent Elements for SPICE Transient Analyses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(3), pp. 429-432, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
16 | Roger B. Dannenberg, Peter G. Hibbard |
A Butler Process for Resource Sharing on Spice Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Inf. Syst. ![In: ACM Trans. Inf. Syst. 3(3), pp. 234-252, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
16 | Di Ma |
A Physical and SPICE-Compatible Model for the MOS Depletion Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3), pp. 349-356, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
16 | Peter Jedele, Haybatolah Khakzar |
Analyse nichtlinearer frequenzabhängiger Übertragungssysteme mit Volterra-Reihen und dem Simulationsprogramm SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simulationstechnik ![In: Simulationstechnik, 3. Symposium Simulationstechnik, Bad Münster am Stein-Ebernburg, 24.-26. September 1985, Proceedings, pp. 404-411, 1985, Springer, 3-540-15700-X. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
16 | A. Stürmer |
Meß- und Auswerte-System (MAUS) und dessen Einsatz zur Bestimmung von Modellparametern zur Simulation mit dem Netzwerkanalyseprogramm SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simulationstechnik ![In: Simulationstechnik, 2. Symposium Simulationstechnik, Wien, 25.-27. September 1984, Proceedings, pp. 171-175, 1984, Springer, 3-540-13393-3. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
16 | Morris Balamut, Ed Kinnen, Rosanne Wyleczuk |
Spice Rack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 1(4), pp. 351-354, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
|
16 | You-Pang Wei |
Large-Scale Circuit Simulation (Vlsi, Spice, Premos, Analysis, Sequencing, Nonlinear, Iteration, Gauss-Seidel) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1983 |
RDF |
|
16 | Ping Yang 0001, Pallab K. Chatterjee |
SPICE Modeling for Small Geometry MOSFET Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1(4), pp. 169-182, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
15 | Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li 0001 |
Accurate clock mesh sizing via sequential quadraticprogramming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 135-142, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, sequential quadratic programming |
15 | Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma |
DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Glob. Optim. ![In: J. Glob. Optim. 44(1), pp. 53-77, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution |
15 | Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001 |
Closed-loop modeling of power and temperature profiles of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 287, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sub-threshold leakage, dynamic power |
15 | He Peng, Chung-Kuan Cheng |
Parallel transistor level circuit simulation using domain decomposition methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 397-402, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Rajesh Garg, Sunil P. Khatri |
Efficient analytical determination of the SEU-induced pulse shape. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 461-467, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Renatas Jakushokas, Eby G. Friedman |
Simultaneous shield and repeater insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 15-20, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
delay, interconnects, noise, power, area |
15 | Debasish Das, William Scott, Shahin Nazarian, Hai Zhou 0001 |
An efficient current-based logic cell model for crosstalk delay analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 627-633, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Bo Hu, C.-J. Richard Shi |
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 883-892, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Amit Goel, Sarma B. K. Vrudhula |
Current source based standard cell model for accurate signal integrity and timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 574-579, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Bao Liu 0001 |
Signal Probability Based Statistical Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 562-567, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Yuichi Tanji, Takayuki Watanabe, Hideki Asai |
Generating stable and sparse reluctance/inductance matrix under insufficient conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 164-169, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ludek Zaloudek, Lukás Sekanina |
Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 320-331, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Victoria Wang, Dejan Markovic |
Linear analysis of random process variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 292-296, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Dimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos |
A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 450-456, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Charles Thangaraj, Tom Chen 0001 |
Design target exploration for meeting time-to-market using pareto analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 364-367, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Massimo Alioto, Massimo Poli, Gaetano Palumbo |
Explicit energy evaluation in RLC tree circuits with ramp inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2865-2868, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Likun Xia, Ian M. Bell, Antony J. Wilkinson |
A novel approach for automated model generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 504-507, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 162-167, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Center and Range, Process Variation, Analog, Spline |
15 | Rouwaida Kanj, Zhuo Li 0001, Rajiv V. Joshi, Frank Liu 0001, Sani R. Nassif |
A Root-Finding Method for Assessing SRAM Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 804-809, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
stability, memory, yield, sram, roots |
15 | Vinay Jain, Payman Zarkesh-Ha |
Analytical Noise-Rejection Model Based on Short Channel MOSFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 401-406, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind |
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 685-691, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Amit Goel, Sarma B. K. Vrudhula |
Statistical waveform and current source based standard cell models for accurate timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 227-230, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
statistical waveform models, process variations, timing analysis |
15 | Peng Li 0001, Zhuo Feng, Emrah Acar |
Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1205-1214, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Saurabh K. Tiwary, Joel R. Phillips |
WAVSTAN: waveform based variational static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1000-1005, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen |
A technique for selecting CMOS transistor orders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 438-443, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Tsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, Kwang-Ting Cheng |
Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 966-969, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Ashesh Rastogi, Wei Chen, Sandip Kundu |
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 712-715, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man |
SWAN: high-level simulation methodology for digital substrate noise generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(1), pp. 23-33, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta |
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2001-2011, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Zhao Li, C.-J. Richard Shi |
A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2868-2881, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi |
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2989-2996, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu |
Time-domain analysis methodology for large-scale RLC circuits and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 49(5), pp. 665-680, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RLC circuits, analog circuit analysis, P/G networks, algorithm complexity, time-domain analysis |
15 | Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff |
Soft delay error analysis in logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 47-52, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Kiyotaka Yamamura, Wataru Kuroki |
An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 408-415, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Xiaolue Lai, Jaijeet S. Roychowdhury |
Macromodelling oscillators using Krylov-subspace methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 527-532, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Douglas R. Hickey, Philip A. Wilsey, Robert J. Hoekstra, Eric R. Keiter, Scott A. Hutchinson, Thomas V. Russo |
Mixed-Signal Simulation with the Simbus Backplane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2-6 April 2006, Huntsville, Alabama, USA, pp. 223-229, 2006, IEEE Computer Society, 0-7695-2559-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Saurabh K. Tiwary, Rob A. Rutenbar |
Faster, parametric trajectory-based macromodels via localized linear reductions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 876-883, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 |
Statistical crosstalk aggressor alignment aware interconnect delay calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 91-97, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Andrei Vladimirescu, Radu Zlatanovici, Paul G. A. Jespers |
Analog circuit synthesis using standard EDA tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Peter Wright, Minghui Fan |
A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 813-817, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Taeyong Je, Yungseon Eo |
Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 419-424, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Hidetomo Nabeshima, Reiko Miyagawa, Yuki Suzuki, Koji Iwanuma |
Rapid Synthesis of Domain-Specific Web Search Engines Based on Semi-Automatic Training-Example Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web Intelligence ![In: 2006 IEEE / WIC / ACM International Conference on Web Intelligence (WI 2006), 18-22 December 2006, Hong Kong, China, pp. 769-772, 2006, IEEE Computer Society, 0-7695-2747-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin |
Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 672-676, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury |
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), pp. 56-64, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong |
IR Drop and Ground Bounce Awareness Timing Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 226-231, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Zhengtao Yu 0002, Xun Liu |
Power Analysis of Rotary Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 150-155, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor |
Framework for Fault Analysis and Test Generation in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1020-1021, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Zhao Li, C.-J. Richard Shi |
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 752-757, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury |
Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 459-464, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Michael Walter Payton, Fat Duen Ho |
A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation PART-I MOSFETs and CMOS inverters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4154-4158, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang |
On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2531-2534, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Michael Walter Payton, Fat Duen Ho |
A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5657-5661, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Ki-Won Song, Kyung-Whan Lee |
Design of Opportunity Tree Framework for Effective Process Improvement based on Quantitative Project Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SERA ![In: Third ACIS International Conference on Software Engineering, Research, Management and Applications (SERA 2005), 11-13 August 2005, Mt. Pleasant, MI, USA, pp. 360-367, 2005, IEEE Computer Society, 0-7695-2297-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan |
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 603-608, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Kartik Mohanram |
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 327-333, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Claudia Kretzschmar, Torsten Bitterlich, Dietmar Müller 0001 |
A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 90-99, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|