| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ignatius Bezzam, Shoba Krishnan |
Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches.  |
VLSID  |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Amin Ghasemazar, Mehran Goli, Ali Afzali-Kusha |
Embedded Complex Floating Point Hardware Accelerator. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Neha Sharan, Santanu Mahapatra |
Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Arunkumar Salimath, Pradeep Karamcheti, Achintya Halder |
A 1 V, Sub-mW CMOS LNA for Low-Power 1 GHz Wide-Band Wireless Applications. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Spencer K. Millican, Kewal K. Saluja |
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhendu Roy, David Z. Pan |
Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthias Beste, Saman Kiamehr, Mehdi Baradaran Tahoori |
Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Yousef Zarei, Mahdi Mosaffa, Siamak Mohammadi |
High-Speed, Low-Power Quasi Delay Insensitive Handshake Circuits Based on FinFET Technology. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Yinlei Yu, Pramod Subramanyan, Nestan Tsiskaridze, Sharad Malik |
All-SAT Using Minimal Blocking Clauses. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | E. M. T. Sirisha, T. Sridevi, D. Thirugnana Murthy |
Process Disturbance Analyzer for Nuclear Reactors. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar 0001, S. Gurunarayanan 0001 |
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Burhan Khurshid, Roohie Naaz Mir |
A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja |
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Meixner, Tobias G. Noll |
Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Shukla, Phong Loi, Ken Pham, Arie Margulis, Kathy Yang, Nagesh Tamarapalli |
Application of Test-View Modeling to Hierarchical ATPG. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Kamalika Datta, Indranil Sengupta 0001 |
All Optical Reversible Multiplexer Design Using Mach-Zehnder Interferometer. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Santu Sardar, K. Ananda Babu |
Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition System. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Sushrant Monga, Shouri Chatterjee |
An Adaptive Inductorless Continuous Time Equalizer for Gigabit Links in 0.13 um CMOS. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar 0001, Vijay Laxmi, Manoj Singh Gaur, Seok-Bum Ko, Mark Zwolinski |
CARM: Congestion Adaptive Routing Method for On Chip Networks. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | K. R. Viveka, Bharadwaj Amrutur |
Energy Efficient Memory Decoder Design for Ultra-low Voltage Systems. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Anand D. Darji, Saurabh Shukla, S. N. Merchant, Arun N. Chandorkar |
Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | |
2014 27th International Conference on VLSI Design, VLSID 2014, and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014 |
VLSID |
2014 |
DBLP BibTeX RDF |
|
| 1 | Sanjay Kumar Wadhwa, Jaideep Banerjee, Rakesh Kumar Gupta |
Low Power Single Amplifier Voltage Regulator. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Sukanta Bhattacharjee, Ansuman Banerjee, Krishnendu Chakrabarty, Bhargab B. Bhattacharya |
Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoke Qin, Prabhat Mishra 0001 |
Scalable Test Generation by Interleaving Concrete and Symbolic Execution. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja |
Temperature Minimization Using Power Redistribution in Embedded Systems. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi |
A Low Power CMOS Imager Based on Distributed Compressed Sensing. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Sundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan |
Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudhakar Singamala, Mandfed Brandl, Sandeep Vernekar, Veereshbabu Vulligadala, Ravikumar Adusumalli, Vijay Ele |
Design of AFE and PWM Drive for Lithium-Ion Battery Management System for HEV/EV System. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Amrita Kumari, Subindu Kumar |
Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative Technique. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Wim Meeus, Tom Vander Aa, Praveen Raghavan, Dirk Stroobandt |
Hard versus Soft Software Defined Radio. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | M. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari |
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Saurabh Kumar Singh, Nitin Bansal |
Output Impedance as Figure of Merit to Predict Transient Performance for Embedded Linear Voltage Regulators. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Misra, N. Sridhar, D. Thirugnana Murthy |
Design and Implementation of Safety Logic with Fine Impulse Test System for a Nuclear Reactor Shutdown System. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim |
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Sharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy |
A Cube-Aware Compaction Method for Scan ATPG. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Cheeranthodi, Santhosh Madhavan, Umesh K. Shukla, Giri Rangan |
Improvements to Negative-C Compensation Based Amplifiers for Broadband Applications. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Pranab Roy, Samadrita Bhattacharya, Rupam Bhattacharyay, Firdousi Jamil Imam, Hafizur Rahaman 0001, Parthasarathi Dasgupta |
A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew Morrison, Nagarajan Ranganathan |
Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Joseph, Nagu R. Dhanwada |
Process Synchronization in Multi-core Systems Using On-Chip Memories. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Israel Koren, Sandip Kundu |
Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Manodipan Sahoo, Prasun Ghosal, Hafizur Rahaman 0001 |
An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagendra Krishnapura |
Tutorial T6A: Pedagogy of Negative Feedback Circuits. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | César A. M. Marcon, Thais Webber, Leticia B. Poehls, Igor K. Pinotti |
Pre-mapping Algorithm for Heterogeneous MPSoCs. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Kun Bian, D. M. H. Walker, Sunil P. Khatri |
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Makarand Shirasgaonkar, Roxanne Vu, Deborah Dressler, Nhat Nguyen, Kambiz Kaviani, Yueyong Wang |
An Adaptive Body-Biased Clock Generation System in 28nm CMOS. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas |
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh |
Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | R. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti |
A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Eshan Singh |
Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect Clustering. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Rangarajan, Pinaki Chakrabarti, Sourav Sahais, Ayan Datta, Adarsh Subramanya |
Tutorial T3B: Engineering Change Order (ECO) Phase Challenges and Methodologies for High Performance Design. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Barun Kumar De, Anupam Chattopadhyay, Ansuman Banerjee |
Tutorial T2B: Cost / Application / Time to Market Driven SoC Design and Manufacturing Strategy. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Chakrabarty, Tsung-Yi Ho |
Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life Sciences. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta |
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Lokesh Siddhu, Amit Mishra 0002, Virendra Singh |
Operand Isolation with Reduced Overhead for Low Power Datapath Design. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Spencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja |
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthik Ramkumar Jeyashankar, Makrand Mahalley, Bharadwaj Amrutur |
A Time-Based Low Voltage Body Temperature Monitoring Unit. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Czutro, Sudhakar M. Reddy, Ilia Polian, Bernd Becker 0001 |
SAT-Based Test Pattern Generation with Improved Dynamic Compaction. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Saha, Tuhina Samanta |
Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingsong Chen, Fan Gu, Lei Zhou 0007, Geguang Pu, Xiao Liu 0004 |
Efficient Two-Phase Approaches for Branch-and-Bound Style Resource Constrained Scheduling. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Nandakishor Yadav, Sunil Dutt, G. K. Sharma 0001 |
A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan |
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | César A. M. Marcon, Ramon Fernandes, Rodrigo Cataldo, Fernando Grando, Thais Webber, Ana Benso, Leticia B. Poehls |
Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Tejasi Pimpalkhute, Sudeep Pasricha |
NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Harshit Agarwal, Yogesh Singh Chauhan, Richard Q. Williams |
BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudhanshu Khanna, Satyanand Nalam, Benton H. Calhoun |
Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Pramod Kaddi, Basireddy Karunakar Reddy, Shiv Govind Singh |
Active Cooling Technique for Efficient Heat Mitigation in 3D-ICs. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Dehbashi, Görschwin Fey |
Debug Automation for Synchronization Bugs at RTL. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Tehranipoor, Domenic Forte |
Tutorial T4: All You Need to Know about Hardware Trojans and Counterfeit ICs. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal |
Global Routing Using Monotone Staircases with Minimal Bends. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Daniel J. Weyer, Christos A. Papachristou, Bhanu Negi |
Knowledge-Guided Methodology for Third-Party Soft IP Analysis. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas |
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu |
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. |
VLSID |
2014 |
DBLP DOI BibTeX RDF |
|
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