Search results for "multiprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link
12	Joan J. Valls, Alberto Ros 0001, Julio Sahuquillo, María Engracia Gómez	PS-Cache: an energy-efficient cache design for chip multiprocessors.	J. Supercomput.	2015	DBLP DOI BibTeX RDF
12	Sara Afshar, Nima Moghaddami Khalilzad, Farhang Nemati, Thomas Nolte	Resource sharing among prioritized real-time applications on multiprocessors.	SIGBED Rev.	2015	DBLP DOI BibTeX RDF
12	Hao Xiao, Ning Wu, Fen Ge, Guanyu Zhu, Lei Zhou 0006	Distributed Synchronization for Message-Passing Based Embedded Multiprocessors.	IEICE Trans. Inf. Syst.	2015	DBLP DOI BibTeX RDF
12	Mohammad Mahdi Keshtegar, Hajar Falahati, Shaahin Hessabi	Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality.	IET Comput. Digit. Tech.	2015	DBLP DOI BibTeX RDF
12	Deli Zhang, Brendan Lynch, Damian Dechev	Queue-Based and Adaptive Lock Algorithms for Scalable Resource Allocation on Shared-Memory Multiprocessors.	Int. J. Parallel Program.	2015	DBLP DOI BibTeX RDF
12	Abdullah Kayi, Olivier Serres, Tarek A. El-Ghazawi	Adaptive Cache Coherence Mechanisms with Producer-Consumer Sharing Optimization for Chip Multiprocessors.	IEEE Trans. Computers	2015	DBLP DOI BibTeX RDF
12	Chenggang Wu 0002, Jin Li, Di Xu, Pen-Chung Yew, Jianjun Li, Zhenjiang Wang	FPS: A Fair-Progress Process Scheduling Policy on Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2015	DBLP DOI BibTeX RDF
12	Dominic DiTomaso, Avinash Karanth Kodi, David W. Matolak, Savas Kaya, Soumyasanta Laha, William Rayess	A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2015	DBLP DOI BibTeX RDF
12	Jagpreet Singh, Sandeep Betha, Bhargav Mangipudi, Nitin Auluck	Contention Aware Energy Efficient Scheduling on Heterogeneous Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2015	DBLP DOI BibTeX RDF
12	Ying Zhang 0016, Lide Duan, Bin Li 0008, Lu Peng 0001, Sadagopan Srinivasan	Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
12	Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie 0001	EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.	ACM Trans. Archit. Code Optim.	2015	DBLP DOI BibTeX RDF
12	Gung-Yu Pan, Jed Yang, Jing-Yang Jou, Bo-Cheng Charles Lai	Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors.	ACM Trans. Embed. Comput. Syst.	2015	DBLP DOI BibTeX RDF
12	Abhisek Pan, Rance Rodrigues, Sandip Kundu	A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors.	ACM Trans. Embed. Comput. Syst.	2015	DBLP DOI BibTeX RDF
12	Hyungjun Kim, Siva Bhanu Krishna Boga, Arseniy Vitkovskiy, Stavros Hadjitheophanous, Paul V. Gratz, Vassos Soteriou, Maria K. Michael	Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors.	ACM Trans. Design Autom. Electr. Syst.	2015	DBLP DOI BibTeX RDF
12	Vítor Schwambach, Sébastien Cleyet-Merle, Alain Issard, Stéphane Mancini	Estimating the Potential Speedup of Computer Vision Applications on Embedded Multiprocessors.	CoRR	2015	DBLP BibTeX RDF
12	Juan Yi, Qingfeng Zhuge, Jingtong Hu, Shouzhen Gu, Mingwen Qin, Edwin Hsing-Mean Sha	Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint.	J. Signal Process. Syst.	2015	DBLP DOI BibTeX RDF
12	Nishit Ashok Kapadia, Venkata Yaswanth Raparti, Sudeep Pasricha	ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors.	NOCS	2015	DBLP DOI BibTeX RDF
12	Raimund Kirner, Saverio Iacovelli, Michael Zolda	Optimised Adaptation of Mixed-Criticality Systems with Periodic Tasks on Uniform Multiprocessors in Case of Faults.	ISORC Workshops	2015	DBLP DOI BibTeX RDF
12	Wen-Hung Huang 0001, Jian-Jia Chen	Response time bounds for sporadic arbitrary-deadline tasks under global fixed-priority scheduling on multiprocessors.	RTNS	2015	DBLP DOI BibTeX RDF
12	Theoni Alexoudi, Dimitrios Fitsios, Pavlos Maniotis, Chris Vagionas, Sotirios Papaioannou 0001, Amalia N. Miliou, George T. Kanellos, Nikos Pleros	WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors.	ICTON	2015	DBLP DOI BibTeX RDF
12	Mwaffaq Otoom, JoAnn M. Paul	Chip-level programming of heterogeneous multiprocessors.	IDT	2015	DBLP DOI BibTeX RDF
12	Jiankang Ren, Linh Thi Xuan Phan	Mixed-Criticality Scheduling on Multiprocessors Using Task Grouping.	ECRTS	2015	DBLP DOI BibTeX RDF
12	Kecheng Yang 0001, James H. Anderson	An Optimal Semi-partitioned Scheduler for Uniform Heterogeneous Multiprocessors.	ECRTS	2015	DBLP DOI BibTeX RDF
12	Anouk Van Laer, Chamath Ellawala, Muhammad Ridwan Madarbux, Philip M. Watts, Timothy M. Jones 0001	Coherence based message prediction for optically interconnected chip multiprocessors.	DATE	2015	DBLP BibTeX RDF
12	Abbas Mazloumi, Mehdi Modarressi	A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors.	DATE	2015	DBLP BibTeX RDF
12	Kathryn E. Gray, Gabriel Kerneis, Dominic P. Mulligan, Christopher Pulte, Susmit Sarkar, Peter Sewell	An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors.	MICRO	2015	DBLP DOI BibTeX RDF
12	Xiaohao Lin, Weichen Liu, Chunming Xiao, Jie Dai, Xianlu Luo, Dan Zhang 0011, Duo Liu, Kaijie Wu 0001, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors.	HPCC/CSS/ICESS	2015	DBLP DOI BibTeX RDF
12	Ryan W. Moore, Bruce R. Childers, Jingling Xue	Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors.	HPCC/CSS/ICESS	2015	DBLP DOI BibTeX RDF
12	Jereme Lamps, Vladimir Adam, David M. Nicol, Matthew Caesar 0001	Conjoining Emulation and Network Simulators on Linux Multiprocessors.	SIGSIM-PADS	2015	DBLP DOI BibTeX RDF
12	Salman Onsori, Arghavan Asad, Özcan Özturk 0001, Mahmood Fathy	Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach.	IGSC	2015	DBLP DOI BibTeX RDF
12	Kecheng Yang 0001, James H. Anderson	On the Soft Real-Time Optimality of Global EDF on Multiprocessors: From Identical to Uniform Heterogeneous.	RTCSA	2015	DBLP DOI BibTeX RDF
12	Zhenmin Li, Avinash Malik, Zoran A. Salcic	Reducing Worst Case Reaction Time of Synchronous Programs on Chip-multiprocessors with Application-Specific TDMA Scheduling.	JTRES	2015	DBLP DOI BibTeX RDF
12	Shuai Zhao 0004, Andy J. Wellings, Stephan Erbs Korsholm	Supporting Multiprocessors in the Icecap Safety-Critical Java Run-Time Environment.	JTRES	2015	DBLP DOI BibTeX RDF
12	Marco Escalante, Andrew B. Kahng, Michael Kishinevsky, Ümit Y. Ogras, Kambiz Samadi	Multi-product floorplan and uncore design framework for chip multiprocessors.	SLIP	2015	DBLP DOI BibTeX RDF
12	Christine Niyizamwiyitira, Lars Lundberg, Håkan Lennerstad	Utilization-Based Schedulability Test of Real-Time Systems on Virtual Multiprocessors.	ICPP Workshops	2015	DBLP DOI BibTeX RDF
12	Ming-Ju Wu, Yan-Ting Chen, Chun-Jen Tsai	Dynamic pipeline-partitioned video decoding on symmetric stream multiprocessors.	ASAP	2015	DBLP DOI BibTeX RDF
12	Milad Ghorbani Moghaddam, Alexandre Yasuo Yamamoto, Cristinel Ababei	Investigation of DVFS based dynamic reliability management for chip multiprocessors.	HPCS	2015	DBLP DOI BibTeX RDF
12	Sara Afshar, Moris Behnam, Reinder J. Bril, Thomas Nolte	Resource sharing in a hybrid partitioned/global scheduling framework for multiprocessors.	ETFA	2015	DBLP DOI BibTeX RDF
12	Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das	An efficient searching mechanism for dynamic NUCA in chip multiprocessors.	VDAT	2015	DBLP DOI BibTeX RDF
12	Jagpreet Singh, Nitin Auluck	Controlled Duplication Scheduling of Real-Time Precedence Tasks on Heterogeneous Multiprocessors.	JSSPP	2015	DBLP DOI BibTeX RDF
12	Aleksandar Simevski	Architectural framework for dynamically adaptable multiprocessors regarding aging, fault tolerance, performance and power consumption.		2015	RDF
12	Milan B. Radulovic, Milo Tomasevic, Veljko M. Milutinovic	Register-Level Communication in Speculative Chip Multiprocessors.	Adv. Comput.	2014	DBLP DOI BibTeX RDF
12	Xiaowen Wu, Yaoyao Ye, Jiang Xu 0001, Wei Zhang 0012, Weichen Liu, Mahdi Nikdast, Xuan Wang 0001	UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
12	Risat Mahmud Pathan, Jan Jonsson	Interference-aware fixed-priority schedulability analysis on multiprocessors.	Real Time Syst.	2014	DBLP DOI BibTeX RDF
12	Björn Andersson, Gurulingesh Raravi	Real-time scheduling with resource sharing on heterogeneous multiprocessors.	Real Time Syst.	2014	DBLP DOI BibTeX RDF
12	Gurulingesh Raravi, Björn Andersson, Vincent Nélis, Konstantinos Bletsas	Task assignment algorithms for two-type heterogeneous multiprocessors.	Real Time Syst.	2014	DBLP DOI BibTeX RDF
12	Sanjoy K. Baruah, Bipasa Chattopadhyay, Haohan Li, Insik Shin	Mixed-criticality scheduling on multiprocessors.	Real Time Syst.	2014	DBLP DOI BibTeX RDF
12	Abdullah Kayi, Olivier Serres, Tarek A. El-Ghazawi	Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors.	Int. J. Parallel Program.	2014	DBLP DOI BibTeX RDF
12	Jian Chen 0030, Arun Arvind Nair, Lizy K. John	Predictive Heterogeneity-Aware Application Scheduling for Chip Multiprocessors.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
12	Yong Li 0009, Rami G. Melhem, Alex K. Jones	A Practical Data Classification Framework for Scalable and High Performance Chip-Multiprocessors.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
12	Zhehui Wang, Jiang Xu 0001, Xiaowen Wu, Yaoyao Ye, Wei Zhang 0012, Mahdi Nikdast, Xuan Wang 0001, Zhe Wang 0003	Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
12	Aparna Mandke Dani, Bharadwaj Amrutur, Y. N. Srikant	Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
12	Usman Mazhar Mirza, Flavius Gruian, Krzysztof Kuchcinski	Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chip.	Comput. Electr. Eng.	2014	DBLP DOI BibTeX RDF
12	Hongya Wang, LihChyun Shu, Wei Yin, Yingyuan Xiao, Jiao Cao	Hyperbolic Utilization Bounds for Rate Monotonic Scheduling on Homogeneous Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2014	DBLP DOI BibTeX RDF
12	Rômulo Silva de Oliveira, Andreu Carminati, Renan Augusto Starke	Using an adversary simulator to evaluate global EDF scheduling of sporadic task sets on multiprocessors.	J. Parallel Distributed Comput.	2014	DBLP DOI BibTeX RDF
12	Hongyin Luo, Shaojun Wei, Deming Chen, Donghui Guo	Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors.	J. Parallel Distributed Comput.	2014	DBLP DOI BibTeX RDF
12	Shirshendu Das, Hemangee K. Kapoor	Victim retention for reducing cache misses in tiled chip multiprocessors.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
12	Alexandre Yasuo Yamamoto, Cristinel Ababei	Unified reliability estimation and management of NoC based chip multiprocessors.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
12	Luis Angel D. Bathen, Nikil D. Dutt	Embedded RAIDs-on-chip for bus-based chip-multiprocessors.	ACM Trans. Embed. Comput. Syst.	2014	DBLP DOI BibTeX RDF
12	Björn Andersson, Gurulingesh Raravi	Provably Good Task Assignment for Two-Type Heterogeneous Multiprocessors Using Cutting Planes.	ACM Trans. Embed. Comput. Syst.	2014	DBLP DOI BibTeX RDF
12	Abbas BanaiyanMofrad, Gustavo Girão, Nikil D. Dutt	NoC-based fault-tolerant cache design in chip multiprocessors.	ACM Trans. Embed. Comput. Syst.	2014	DBLP DOI BibTeX RDF
12	Nizar Dahir, Ra'ed Al-Dujaily, Terrence S. T. Mak, Alex Yakovlev	Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.	ACM Trans. Embed. Comput. Syst.	2014	DBLP DOI BibTeX RDF
12	Gurulingesh Raravi, Vincent Nélis	Task Assignment Algorithms for Heterogeneous Multiprocessors.	ACM Trans. Embed. Comput. Syst.	2014	DBLP DOI BibTeX RDF
12	Gung-Yu Pan, Jing-Yang Jou, Bo-Cheng Lai	Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
12	Da-Cheng Juan, Siddharth Garg, Diana Marculescu	Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
12	Guangmo Tong, Cong Liu 0005	Supporting Soft Real-Time Sporadic Task Systems on Heterogeneous Multiprocessors with No Utilization Loss.	CoRR	2014	DBLP BibTeX RDF
12	Shun-Chi Yu	Elucidating multiprocessors flow shop scheduling with dependent setup times using a twin particle swarm optimization.	Appl. Soft Comput.	2014	DBLP DOI BibTeX RDF
12	Poongothai Marimuthu, Rajeswari Arumugam, V. Kanishkan	A heuristic based real time task assignment algorithm for heterogeneous multiprocessors.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
12	Cong Liu 0005, James H. Anderson	Supporting soft real-time parallel applications on multiprocessors.	J. Syst. Archit.	2014	DBLP DOI BibTeX RDF
12	Thomas E. Anderson, Brian N. Bershad, Edward D. Lazowska, Henry M. Levy	Thread Management for Shared-Memory Multiprocessors.	Computing Handbook, 3rd ed. (1)	2014	DBLP BibTeX RDF
12	Harsh Arora, Rijubrata Mukherjee, Abhijit Bej, Hillol Adak	Directory based cache coherence modeller in multiprocessors: Medium insight.	ICACCI	2014	DBLP DOI BibTeX RDF
12	Xiang Pan, Radu Teodorescu	Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors.	PACT	2014	DBLP DOI BibTeX RDF
12	Millad Ghane, Mohammad Arjomand, Hamid Sarbazi-Azad	An Opto-electrical NoC with Traffic Flow Prediction in Chip Multiprocessors.	PDP	2014	DBLP DOI BibTeX RDF
12	Bipasa Chattopadhyay, Sanjoy K. Baruah	Limited-Preemption Scheduling on Multiprocessors.	RTNS	2014	DBLP DOI BibTeX RDF
12	Kecheng Yang 0001, James H. Anderson	Soft Real-Time Semi-Partitioned Scheduling with Restricted Migrations on Uniform Heterogeneous Multiprocessors.	RTNS	2014	DBLP DOI BibTeX RDF
12	Malèk Channoufi, Pierre Lecoy, Rabah Attia, Sofien Mhatli, Bruno Delacressonniere	Nanophotonic network on chip for next generation of multiprocessors system on chip.	CSNDSP	2014	DBLP DOI BibTeX RDF
12	Mamata Dalui, Biplab K. Sikdar	CA Based Scalable Protocol Processor for Chip Multiprocessors.	ISED	2014	DBLP DOI BibTeX RDF
12	David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel A. Jiménez	B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors.	MICRO	2014	DBLP DOI BibTeX RDF
12	Aleksandar Simevski, Rolf Kraemer, Milos Krstic	Investigating Core-Level N-Modular Redundancy in Multiprocessors.	MCSoC	2014	DBLP DOI BibTeX RDF
12	Onur Derin, Leandro Fiorin	Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors.	ARCS Workshops	2014	DBLP BibTeX RDF
12	Yuan Yao 0009, Zhonghai Lu	Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems.	ASP-DAC	2014	DBLP DOI BibTeX RDF
12	Nilufar Ferdous, Byeong Kil Lee, Eugene John	Performance enhancement in shared-memory multiprocessors using dynamically classified sharing information.	IPCCC	2014	DBLP DOI BibTeX RDF
12	Jagpreet Singh, Nitin Auluck	DVFS and duplication based scheduling for optimizing power and performance in heterogeneous multiprocessors.	SpringSim (HPS)	2014	DBLP BibTeX RDF
12	Junli Gu, Bradford M. Beckmann, Ting Cao, Yu Hu	iCHAT: Inter-cache Hardware-Assistant Data Transfer for Heterogeneous Chip Multiprocessors.	NAS	2014	DBLP DOI BibTeX RDF
12	Bryan C. Ward, James H. Anderson	Multi-resource Real-Time Reader/Writer Locks for Multiprocessors.	IPDPS	2014	DBLP DOI BibTeX RDF
12	Di Zhu 0002, Lizhong Chen, Siyu Yue, Timothy Mark Pinkston, Massoud Pedram	Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors.	IPDPS	2014	DBLP DOI BibTeX RDF
12	Edward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum	Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies.	ICS 25th Anniversary	2014	DBLP DOI BibTeX RDF
12	Jichuan Chang, Gurindar S. Sohi	Author retrospective for cooperative cache partitioning for chip multiprocessors.	ICS 25th Anniversary	2014	DBLP DOI BibTeX RDF
12	Tao Yang 0009, Apostolos Gerasoulis	Author retrospective for PYRROS: static task scheduling and code generation for message passing multiprocessors.	ICS 25th Anniversary	2014	DBLP DOI BibTeX RDF
12	Jianqing Xiao, Pengwei Lv, Mian Lou, Xunying Zhang, Xubang Shen	A task-level superscalar microarchitecture for large scale chip multiprocessors.	RTCSA	2014	DBLP DOI BibTeX RDF
12	Jaewoo Lee, Kieu-My Phan, Xiaozhe Gu, Jiyeon Lee, Arvind Easwaran, Insik Shin, Insup Lee 0001	MC-Fluid: Fluid Model-Based Mixed-Criticality Scheduling on Multiprocessors.	RTSS	2014	DBLP DOI BibTeX RDF
12	Hamza Gharsellaoui, Mohamed Khalgui, Samir Ben Ahmed	Preemptive Hard Real-time Scheduling of Reconfigurable OS Tasks on Multiprocessors Embedded Control Systems.	PECCS	2014	DBLP DOI BibTeX RDF
12	Mourad Elhadef	A Machine Learning Approach for Self-Diagnosing Multiprocessors Systems under the Generalized Comparison Model.	UIC/ATC/ScalCom	2014	DBLP DOI BibTeX RDF
12	Kecheng Yang 0001, James H. Anderson	Optimal GEDF-based schedulers that allow intra-task parallelism on heterogeneous multiprocessors.	ESTIMedia	2014	DBLP DOI BibTeX RDF
12	Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie 0001	EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.	ISLPED	2014	DBLP DOI BibTeX RDF
12	Pavlos Maniotis, D. Fitsios, George T. Kanellos, Nikos Pleros	A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors.	OFC	2014	DBLP DOI BibTeX RDF
12	Jurrien de Klerk, Sumeet S. Kumar, René van Leuken 0001	Cache Balancer: Access Rate and Pain Based Resource Management for Chip Multiprocessors.	CANDAR	2014	DBLP DOI BibTeX RDF
12	Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Guanyu Zhu	Distributed synchronization for message-passing based embedded multiprocessors.	ASAP	2014	DBLP DOI BibTeX RDF
12	Chuanlei Zheng, Shuai Wang 0006	Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors.	DFT	2014	DBLP DOI BibTeX RDF
12	Ying Zhang 0016, Lide Duan, Bin Li 0008, Lu Peng 0001, Sadagopan Srinivasan	Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors.	ISQED	2014	DBLP DOI BibTeX RDF