Search results for "pipelining"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Jae-Beom Lee, Byeong Gi Lee	Transform domain filtering based on pipelining structure.	IEEE Trans. Signal Process.	1992	DBLP DOI BibTeX RDF
15	Devinder Kaur 0001	Hierarchical Hypernet for Pipelining.	Comput. J.	1992	DBLP DOI BibTeX RDF
15	Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri	A non-deterministic scheduler for a software pipelining compiler.	MICRO	1992	DBLP DOI BibTeX RDF
15	Randall M. Lee, Vicki H. Allan	Advanced Software Pipelining and the Program Dependence Graph.	SPDP	1992	DBLP DOI BibTeX RDF
15	Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin	An effective methodology for functional pipelining.	ICCAD	1992	DBLP DOI BibTeX RDF
15	H. Fatih Ugurdag, Christos A. Papachristou	ALMP: A Shifting Memory Architecture for Loop Pipelining.	ICCD	1992	DBLP DOI BibTeX RDF
15	Miodrag Potkonjak, Jan M. Rabaey	Pipelining: just another transformation.	ASAP	1992	DBLP DOI BibTeX RDF
15	Fabian Klass, Johannes M. Mulder	Use of CMOS Technology in Wave Pipelining.	VLSI Design	1992	DBLP DOI BibTeX RDF
15	Arthur Abnous, Nader Bagherzadeh	Pipelining and bypassing in a VLIW processor.	ISCA	1992	DBLP DOI BibTeX RDF
15	Reiner Müller	Implementierung von Algorithmen zur Optimierung von Schleifen mit Hilfe von Software-Pipelining-Techniken	Forschungsberichte, TU Munich	1991	RDF
15	Keshab K. Parhi	Pipelining in dynamic programming architectures.	IEEE Trans. Signal Process.	1991	DBLP DOI BibTeX RDF
15	Guang R. Gao	A code mapping scheme for dataflow software pipelining.		1991	RDF
15	C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III	Theoretical and Practical Issues in CMOS Wave Pipelining.	VLSI	1991	DBLP BibTeX RDF
15	Albert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh	Hierarchical Retiming Including Pipelining.	VLSI	1991	DBLP BibTeX RDF
15	Bogong Su, Jian Wang 0046	GURPR*: A New Global Software Pipelining Algorithm.	MICRO	1991	DBLP DOI BibTeX RDF
15	Jan Hoogerbrugge, Henk Corporaal, Hans M. Mulder	Software Pipelining for Transport-Triggered Architectures.	MICRO	1991	DBLP DOI BibTeX RDF
15	Suneel Jain	Circular Scheduling: A New Technique to Perform Software Pipelining.	PLDI	1991	DBLP DOI BibTeX RDF
15	Rajinder Jit Singh, John V. McCanny	A wave digital filter three-port adaptor with fine grained pipelining.	ASAP	1991	DBLP DOI BibTeX RDF
15	Wayne W. C. Luk	Pipelining and transposing heterogeneous array circuits.	ASAP	1991	DBLP DOI BibTeX RDF
15	Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin	Scheduling for Functional Pipelining and Loop Winding.	DAC	1991	DBLP DOI BibTeX RDF
15	C. Y. Roger Chen, Michael Z. Moricz	Datapath Scheduling for Two-Level Pipelining.	DAC	1991	DBLP DOI BibTeX RDF
15	David T. Barnard, David B. Skillicorn	Pipelining Tree-Structured Algorithms on Simd Architectures.	Inf. Process. Lett.	1990	DBLP DOI BibTeX RDF
15	Pradeep K. Dubey, Michael J. Flynn	Optimal Pipelining.	J. Parallel Distributed Comput.	1990	DBLP DOI BibTeX RDF
15	R. L. Bailey, Ravi Mukkamala	Pipelining Data Compression Algorithms.	Comput. J.	1990	DBLP DOI BibTeX RDF
15	J. P. C. F. H. Smeets, Willem J. Withagen, M. P. J. Stevens	Pipelining a memory based CISC processor.	Microprocessing and Microprogramming	1990	DBLP DOI BibTeX RDF
15	Anurag Kumar 0001, Robert G. Cole	Comparative Performance of Interleaved and Non-Interleaved Pipelining in LAPD Terminal Adaptors.	INFOCOM	1990	DBLP DOI BibTeX RDF
15	Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man	Combined hardware selection and pipelining in high performance data-path design.	ICCD	1990	DBLP DOI BibTeX RDF
15		Pipelining through Dynamic Control ROM.	SIGARCH Comput. Archit. News	1989	DBLP DOI BibTeX RDF
15	Hui Cheng	Vector Pipelining, Chaining, and Speed on the IBM 3090 and Cray X-MP.	Computer	1989	DBLP DOI BibTeX RDF
15	Keshab K. Parhi, David G. Messerschmitt	Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition.	IEEE Trans. Acoust. Speech Signal Process.	1989	DBLP DOI BibTeX RDF
15	J. A. K. S. Jayasinghe, O. E. Herrmann	Two-level Pipelining of Systolic Array Graphics Engines.	Advances in Computer Graphics Hardware	1989	DBLP DOI BibTeX RDF
15	Derek C. Wong, Giovanni De Micheli, Michael J. Flynn	Inserting active delay elements to achieve wave pipelining.	ICCAD	1989	DBLP DOI BibTeX RDF
15	Ajoy Kumar Datta, Sukumar Ghosh, Muhundan Gopalan, Ahmed K. Elmagarmid	Pipelining and concurrency in graphics and image-processing applications.	Comput. Syst. Sci. Eng.	1988	DBLP BibTeX RDF
15	Chung-Ta King, Lionel M. Ni	Large-grain pipelining on hypercube multiprocessors.	C³P	1988	DBLP DOI BibTeX RDF
15	Roger F. Woods, Simon C. Knowles, John V. McCanny, John G. McWhirter	Systolic IIR filters with bit level pipelining.	ICASSP	1988	DBLP DOI BibTeX RDF
15	Hidenori Kimura, T. Osada	Canonical pipelining of lattice filters.	IEEE Trans. Acoust. Speech Signal Process.	1987	DBLP DOI BibTeX RDF
15	Erik Sandewall	The Pipelining Transformation on Plans for Manufacturing Cells with Robots.	IJCAI	1987	DBLP BibTeX RDF
15	Guang R. Gao	Maximum pipelining linear recurrence on static data flow computers.	Int. J. Parallel Program.	1986	DBLP DOI BibTeX RDF
15	H. V. Jagadish, Robert G. Mathews, Thomas Kailath, John A. Newkirk	A Study of Pipelining in Computing Arrays.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF
15	Yvon Jégou, André Seznec	Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments.	J. Parallel Distributed Comput.	1986	DBLP DOI BibTeX RDF
15	Stanley Y. W. Su, Krishna P. Mikkilineni, Raymond A. Liuzzi, Yuan-Chieh Chow	A Distributed Query Processing Strategy Using Decomposition, Pipelining and Intermediate Result Sharing Techniques.	ICDE	1986	DBLP DOI BibTeX RDF
15	Robert A. Mueller, Bogong Su, Michael R. Duda, Brian L. Plomondon	A case study in signal processing microprogramming using the URPR software pipelining technique.	MICRO	1986	DBLP DOI BibTeX RDF
15	Bogong Su, Shiyuan Ding, Jinshi Xia	URPR - An extension of URCR for software pipelining.	MICRO	1986	DBLP DOI BibTeX RDF
15	Mehdi Hatamian, Glenn L. Cash	High speed signal processing, pipelining, and VLSI.	ICASSP	1986	DBLP DOI BibTeX RDF
15	Yvon Jégou, André Seznec	Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments.	ICPP	1986	DBLP BibTeX RDF
15	Jaime H. Moreno, Tomás Lang	Replication and Pipelining in Multiple-Instance Algorithms.	ICPP	1986	DBLP BibTeX RDF
15	J. Dean Brock, Amos R. Omondi	Shared Pipelines: Effective Pipelining in Multiprocessor Systems.	ICPP	1986	DBLP BibTeX RDF
15	Steven R. Kunkel, James E. Smith 0001	Optimal Pipelining in Supercomputers.	ISCA	1986	DBLP DOI BibTeX RDF
15	David M. Proulx	Applications of pipelining to firmware.	MICRO	1984	DBLP BibTeX RDF
15	Jack B. Dennis, Guang R. Gao	Maximum Pipelining of Array Operations on Static Data Flow Machine.	ICPP	1983	DBLP BibTeX RDF
15	Patrick V. McGregor	Concentrator Modeling With Pipelining Arrivals Compensation.	SIGMETRICS	1982	DBLP DOI BibTeX RDF
15	Dennis Gannon	Pipelining array computations for MIMD parallelism: a function specification.	ICPP	1982	DBLP BibTeX RDF
15	J. Robert Jump, Sudhir Ahuja	Effective Pipelining of Digital Systems.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF
15	P. Bruce Berra, Ashok K. Singhania	A Multiple Associative Memory Organization for Pipelining a Directory to a Very Large Data Base - Abstract.	SIGIR Forum	1976	DBLP DOI BibTeX RDF
15	Joachim Swoboda	Was ist pipelining?	Elektron. Rechenanlagen	1975	DBLP DOI BibTeX RDF
15	Leonard E. Shar, Edward S. Davidson	A multiminiprocessor system implemented through pipelining.	Computer	1974	DBLP DOI BibTeX RDF
15	Jerome M. Kurtzberg, Raymond D. Villani	A Balanced Pipelining Approach to Multiprocessing on an Instruction Stream Level.	IEEE Trans. Computers	1973	DBLP DOI BibTeX RDF
15	Wolfgang Händler	The concept of Marco-Pipelining with high availability.	Elektron. Rechenanlagen	1973	DBLP DOI BibTeX RDF
15	Thomas G. Hallin, Michael J. Flynn	Pipelining of Arithmetic Functions.	IEEE Trans. Computers	1972	DBLP DOI BibTeX RDF
15	Thomas G. Hallin, Michael J. Flynn	Pipelining of arithmetic functions.	IEEE Symposium on Computer Arithmetic	1972	DBLP DOI BibTeX RDF
15	Guangming Tan, Ninghui Sun, Guang R. Gao	Improving Performance of Dynamic Programming via Parallelism and Locality on Multicore Architectures.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
15	Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería	On reducing misspeculations in a pipelined scheduler.	IPDPS	2009	DBLP DOI BibTeX RDF
15	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	Mapping stream programs onto heterogeneous multiprocessor systems.	CASES	2009	DBLP DOI BibTeX RDF	partitioning, multicore, convexity, stream programming
15	Zhenyu Liu 0001, Lingfeng Li, Yang Song 0002, Shen Li, Satoshi Goto, Takeshi Ikenaga	Motion Feature and Hadamard Coefficient-Based Fast Multiple Reference Frame Motion Estimation for H.264.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
15	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	Two-Dimensional Schemes for Clocking/Timing of QCA Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
15	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk	Implementation of Wave-Pipelined Interconnects in FPGAs.	NOCS	2008	DBLP DOI BibTeX RDF
15	Hui Liu 0006, Zili Shao, Meng Wang 0005, Ping Chen	Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip.	ECRTS	2008	DBLP DOI BibTeX RDF
15	Jason Cong, Yi Zou	Lithographic aerial image simulation with FPGA-based hardwareacceleration.	FPGA	2008	DBLP DOI BibTeX RDF	co-processor acceleration, lithography simulation, FPGA
15	Min Li 0001, David Novo, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor	Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications.	DATE	2008	DBLP DOI BibTeX RDF
15	Miao Wang, Rongcai Zhao, Jianmin Pang, Guoming Cai	Reconstructing Control Flow in Modulo Scheduled Loops.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	register rotation, modulo scheduling, decompilation, predication execution, conditional branches
15	Blaz Lampreht, Luka Stepancic, Igor Vizec, Bostjan Zankar, Miha Mraz, Iztok Lebar Bajec, Primoz Pecar	Quantum-Dot Cellular Automata Serial Comparator.	DSD	2008	DBLP DOI BibTeX RDF
15	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Optimization technique for flip-flop inserted global interconnect.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Michele Boreale, Roberto Bruni, Rocco De Nicola, Michele Loreti	Sessions and Pipelines for Structured Service Programming.	FMOODS	2008	DBLP DOI BibTeX RDF
15	Michael Gschwind	The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
15	Y. Yi, In-Cheol Park	High-Speed H.264/AVC CABAC Decoding.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
15	Love Singhal, Elaheh Bozorgzadeh, David Eppstein	Interconnect Criticality-Driven Delay Relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Xiaotong Zhuang, Santosh Pande	Allocating architected registers through differential encoding.	ACM Trans. Program. Lang. Syst.	2007	DBLP DOI BibTeX RDF	architected register, differential encoding, Register allocation
15	Jonathan Ezekiel, Gerald Lüttgen, Gianfranco Ciardo	Parallelising Symbolic State-Space Generators.	CAV	2007	DBLP DOI BibTeX RDF
15	Mathys Walma	Pipelined Cyclic Redundancy Check (CRC) Calculation.	ICCCN	2007	DBLP DOI BibTeX RDF
15	Eric L. Hill, Mikko H. Lipasti	Transparent mode flip-flops for collapsible pipelines.	ICCD	2007	DBLP DOI BibTeX RDF
15	Gorn Tepvorachai, Christos A. Papachristou	A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure.	AHS	2007	DBLP DOI BibTeX RDF
15	Carolina Ribeiro Xavier, Rafael Sachetto Oliveira, Vinícius da Fonseca Vieira, Rodrigo Weber dos Santos, Wagner Meira Jr.	Multi-level Parallelism in the Computational Modeling of the Heart.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
15	Bangyu Wu, Chi-Hung Chi, Zhe Chen	Resource Allocation Based On Workflow For Enhancing the Performance of Composite Service.	IEEE SCC	2007	DBLP DOI BibTeX RDF
15	Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen	Hardware architecture design of an H.264/AVC video codec.	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Florian Stock, Andreas Koch 0001	Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays.	FPL	2006	DBLP DOI BibTeX RDF
15	Suraj Pandey, Ho Seok Kim, Sang Hun Eo, Hae-Young Bae	Systolic Query Processing for Aggregation in Sensor Networks.	UIC	2006	DBLP DOI BibTeX RDF
15	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
15	Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty	A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm.	VLSI Design	2006	DBLP DOI BibTeX RDF
15	Lok-Kee Ting, Roger F. Woods, C. F. N. Cowan	Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
15	Keshab K. Parhi	Design of multigigabit multiplexer-loop-based decision feedback equalizers.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
15	Stavros Harizopoulos, Vladislav Shkapenyuk, Anastassia Ailamaki	QPipe: A Simultaneously Pipelined Relational Query Engine.	SIGMOD Conference	2005	DBLP DOI BibTeX RDF
15	Mehrdad Reshadi, Daniel Gajski	A cycle-accurate compilation algorithm for custom pipelined datapaths.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	NISC, cycle-accurate compiler, scheduling
15	Xiaotong Zhuang, Santosh Pande	Differential register allocation.	PLDI	2005	DBLP DOI BibTeX RDF	architected register, differential dncoding, register allocation
15	Bita Gorjiara, Daniel D. Gajski	Custom Processor Design Using NISC: A Case-Study on DCT algorithm.	ESTIMedia	2005	DBLP DOI BibTeX RDF
15	Xiaoyao Liang, Akshay Athalye, Sangjin Hong	Dynamic coarse grain dataflow reconfiguration technique for real-time systems design.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
15	Moonseok Kang, Wonyong Sung	Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
15	Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee	An H.264/AVC decoder with 4×4-block level pipeline.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
15	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Register Constrained Modulo Scheduling.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code
15	Alireza Hodjat, Ingrid Verbauwhede	Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.	ISVLSI	2004	DBLP DOI BibTeX RDF
15	Magesh Sadasivam, Sangjin Hong	Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow.	ISVLSI	2004	DBLP DOI BibTeX RDF