Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Proshanta Saha	Automatic Software Hardware Co-Design for Reconfigurable Computing Systems.	FPL	2007	DBLP DOI BibTeX RDF
21	Heiner Giefers, Marco Platzner	A Many-core Implementation based on the Reconfigurable Mesh Model.	FPL	2007	DBLP DOI BibTeX RDF
21	Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann	A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
21	Kang Sun, Xuezeng Pan, Jimin Wang, Lingdi Ping	PAD: A Design Space Exploration Model For Reconfigurable Systems.	ITNG	2007	DBLP DOI BibTeX RDF
21	Ying Chen, Simon Y. Chen	Cost-Driven Hybrid Configuration Prefetching for Partial Reconfigurable Coprocessor.	IPDPS	2007	DBLP DOI BibTeX RDF
21	Florian Dittmann 0001, Marcelo Götz, Achim Rettberg	Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems.	IPDPS	2007	DBLP DOI BibTeX RDF
21	Mingxian Jin, Johnnie W. Baker	On the Power of the Multiple Associative Computing (MASC) Model Related to That of Reconfigurable Bus-Based Models.	IPDPS	2007	DBLP DOI BibTeX RDF
21	Jim Tørresen, Kyrre Glette	Improving Flexibility in On-Line Evolvable Systems by Reconfigurable Computing.	ICES	2007	DBLP DOI BibTeX RDF
21	Proshanta Saha, Tarek A. El-Ghazawi	Software/Hardware Co-Scheduling for Reconfigurable Computing Systems.	FCCM	2007	DBLP DOI BibTeX RDF
21	Li Chia, Chi-Sheng Shih 0001	Template-based Runtime Reconfiguration Scheduling for Partial Reconfigurable SoC.	RTCSA	2007	DBLP DOI BibTeX RDF
21	Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi	System-Level Design for Partially Reconfigurable Hardware.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Wim Vanderbauwhede	Separation of Data flow and Control flow in Reconfigurable Multi-core SoCs using the Gannet Service-based Architecture.	AHS	2007	DBLP DOI BibTeX RDF
21	Björn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen	Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application.	AHS	2007	DBLP DOI BibTeX RDF
21	Richard Hough, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, John W. Lockwood, Jason E. Fritts	Empirical performance assessment using soft-core processors on reconfigurable hardware.	Experimental Computer Science	2007	DBLP DOI BibTeX RDF
21	Vincenzo Grassi, Raffaela Mirandola, Antonino Sabetta	A model-driven approach to performability analysis of dynamically reconfigurable component-based systems.	WOSP	2007	DBLP DOI BibTeX RDF	performability, model-driven development, dynamic reconfiguration
21	Sohaib Majzoub, Hassan B. Diab	Mapping and Performance Analysis of Lookup Table Implementations on Reconfigurable Platform.	AICCSA	2007	DBLP DOI BibTeX RDF
21	K. N. Vikram, Vinita Vasudevan	Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Juanjo Noguera, Rosa M. Badia	System-level power-performance tradeoffs for reconfigurable computing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Virtual memory window for application-specific reconfigurable coprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Miguel A. Vega-Rodríguez, Juan Antonio Gómez Pulido, Juan Manuel Sánchez-Pérez, José M. Granado Criado, Manuel Rubio del Solar	Reconfigurable Computing and Parallelism for Implementing and Accelerating Evolutionary Algorithms.	Parallel Evolutionary Computations	2006	DBLP DOI BibTeX RDF
21	Leipo Yan, Thambipillai Srikanthan, Niu Gang	Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures.	LCTES	2006	DBLP DOI BibTeX RDF	CGRA, VLIW, hardware/software partitioning, delay estimation, area estimation
21	Didier Bourse, Karim El-Khazen, Al Lee, Dragan Boscovic	Business Models of End-to-End Reconfigurable Systems.	VTC Spring	2006	DBLP DOI BibTeX RDF
21	Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay	System-level scheduling on instruction cell based reconfigurable systems.	DATE	2006	DBLP DOI BibTeX RDF
21	Ying Wei 0002, Hua Tang, Alex Doboli	Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems.	DATE	2006	DBLP DOI BibTeX RDF
21	Pao-Ann Hsiung, Chun-Hsian Huang, Chih-Feng Liao	Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems.	FPL	2006	DBLP DOI BibTeX RDF
21	Arnaud Lagger, Andres Upegui, Eduardo Sanchez, Iván González	Self-Reconfigurable Pervasive Platform for Cryptographic Application.	FPL	2006	DBLP DOI BibTeX RDF
21	Hayden Kwok-Hay So, Robert W. Brodersen	Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support.	FPL	2006	DBLP DOI BibTeX RDF
21	Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura	Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells.	FPL	2006	DBLP DOI BibTeX RDF
21	Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.	A fast SAT solver algorithm best suited to reconfigurable hardware.	SBCCI	2006	DBLP DOI BibTeX RDF	formal verification, SAT, CNF, DPLL
21	Milene Barbosa Carvalho, Luís F. W. Góes, Carlos Augusto Paiva da Silva Martins	Dynamically reconfigurable cache architecture using adaptive block allocation policy.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Sebastian Lange, Martin Middendorf	Multi-level reconfigurable architectures in the switch model.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Mohamed Taher, Tarek A. El-Ghazawi	Exploiting processing locality through paging configurations in multitasked reconfigurable systems.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Farhad Mehdipour, Morteza Saheb Zamani, Hamid Reza Ahmadifar, Mehdi Sedighi, Kazuaki J. Murakami	Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi	An optically differential reconfigurable gate array with a holographic memory.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Sascha Uhrig, Stefan Maier, Georgi Kuzmanov, Theo Ungerer	Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Qin Wang 0004, Ang Li, Zhancai Li, Yong Wan	A Design and Implementation of Reconfigurable Architecture for Neural Networks Based on Systolic Arrays.	ISNN (2)	2006	DBLP DOI BibTeX RDF
21	John H. Reif, Sam Slee	Asymptotically Optimal Kinodynamic Motion Planning for Self-reconfigurable Robots.	WAFR	2006	DBLP DOI BibTeX RDF
21	Björn Griese, Boris Kettelhoit, Mario Porrmann	Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors.	PARELEC	2006	DBLP DOI BibTeX RDF
21	Kang Sun, Lingdi Ping, Jiebing Wang, Zugen Liu, Xuezeng Pan	Design of a Reconfigurable Cryptographic Engine.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
21	Hanho Lee, Chang-Seok Choi	Implementation of a FIR Filter on a Partial Reconfigurable Platform.	KES (3)	2006	DBLP DOI BibTeX RDF
21	Rawat Siripokarpirom	Platform Development for Run-Time Reconfigurable Co-Emulation.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
21	Lukás Sekanina	On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	FPGA, evolutionary algorithms, dependability, evolvable hardware
21	Claudio Mucci, Massimo Bocchi, Mario Toma, Fabio Campi	A case-study on multimedia applications for the XiRisc reconfigurable processor.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Evangelos F. Stefatos, I. Bravos, Tughrul Arslan	Low-power implementation of FIR filters within an adaptive reconfigurable architecture.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Franklin Bien, Youngsik Hur, Moonkyun Maeng, Hyoungsoo Kim, Edward Gebara, Joy Laskar	A reconfigurable fully-integrated 0.18µm CMOS feed forward equalizer IC for 10-Gb/sec backplane links.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Tughrul Arslan, Nakul Haridas, Erfu Yang, Ahmet T. Erdogan, Nick Barton, Anthony J. Walton, John S. Thompson, Adrian Stoica, Tanya Vladimirova, Klaus D. McDonald-Maier, W. Gareth J. Howells	ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace-Based Monitoring and Diagnostics.	AHS	2006	DBLP DOI BibTeX RDF
21	Raphael Fonte Boa, Dulcinéia Oliveira da Penha, Alexandre Marques Amaral, Márcio Oliveira Soares de Souza, Carlos Augusto Paiva da Silva Martins, Petr Yakovlevitch Ekel	RCMP: A Reconfigurable Chip-Multiprocessor Architecture.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
21	Ambrose Chu, Mihai Sima	Reconfigurable RSA Cryptography for Embedded Devices.	CCECE	2006	DBLP DOI BibTeX RDF
21	Ted Huffmire, Shreyas Prasad, Timothy Sherwood, Ryan Kastner	Policy-Driven Memory Protection for Reconfigurable Hardware.	ESORICS	2006	DBLP DOI BibTeX RDF	Embedded Systems, Computer Security, Security Policies, Policy Languages, Reference Monitors, Separation Kernels
21	Kang Sun, Xuezeng Pan, Jiebing Wang, Jimin Wang	Design of A Novel Asynchronous Reconfigurable Architecture for Cryptographic Applications.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF
21	Kentaro Oda, Hiroki Najima, Yoshihiro Yasutake, Takaichi Yoshida	A Simple, Safe Reconfigurable Object Model with Loosely-Coupled Communication.	AINA (1)	2006	DBLP DOI BibTeX RDF
21	Stefan Mohl	Innovative technologies I - Using FPGAs in supercomputers: breaking with reconfigurable computing.	SC	2006	DBLP DOI BibTeX RDF
21	Tarek A. El-Ghazawi, Duncan A. Buell, Volodymyr V. Kindratenko, Kris Gaj	M03 - Reconfigurable supercomputing.	SC	2006	DBLP DOI BibTeX RDF
21	Ben Cordes, Miriam Leeser, Eric L. Miller 0001, Richard W. Linderman	Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer.	SC	2006	DBLP DOI BibTeX RDF
21	Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo	Efficient datapath merging for partially reconfigurable architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Alberto La Rosa, Luciano Lavagno, Claudio Passerone	Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon	Dynamic hardware multiplexing for coarse grain reconfigurable architectures.	FPGA	2005	DBLP DOI BibTeX RDF
21	Michael Attig, John W. Lockwood	A framework for rule processing in reconfigurable network systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
21	Benoît Miramond, Jean-Marc Delosme	Design Space Exploration for Dynamically Reconfigurable Architectures.	DATE	2005	DBLP DOI BibTeX RDF
21	Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen	SystemC-based Design Methodology for Reconfigurable System-on-Chip.	DSD	2005	DBLP DOI BibTeX RDF
21	Fredy Rivera, Milagros Fernández, Nader Bagherzadeh	An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures.	DSD	2005	DBLP DOI BibTeX RDF
21	John C. Gallagher, Sanjay K. Boddhu, Saranyan A. Vigraham	A reconfigurable continuous time recurrent neural network for evolvable hardware applications.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
21	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A function generator-based reconfigurable system.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	Carles Riba Romeva, Roberto Pérez, A. Jorge L. Sánchez, María D. Domínguez, Joaquín Aca, G. Arturo Molina	A Concurrent Approach to Design of Reconfigurable Machine Tools to Process Bamboo.	CDVE	2005	DBLP DOI BibTeX RDF	Bamboo, Reconfigurability, Machine Tool, Concurrent Design
21	Timothy O'Sullivan, Richard Studdert	Handheld Medical Devices Negotiating for Reconfigurable Resources Using Agents.	CBMS	2005	DBLP DOI BibTeX RDF
21	Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon	Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Evangelos F. Stefatos, Wei Han 0001, Tughrul Arslan, Robert Thomson 0003	Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Melissa C. Smith, Jeffrey S. Vetter, Xuejun Liang	Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima, Paulo Romero Martins Maciel, Carlos A. Valderrama, Abel Guilhermino Silva-Filho, Paulo Sérgio B. do Nascimento	A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Imran Ahmed 0001, Tughrul Arslan, Sajid Baloch, Ian Underwood, Robin Woodburn	Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Christiane V. Pousa, Luís F. W. Góes, Dulcinéia Oliveira da Penha, Carlos Augusto Paiva da Silva Martins	Reconfigurable Sequential Consistency Algorithm.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Pradeep Nalabalapu, Ron Sass	Bandwidth Management with a Reconfigurable Data Cache.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Christiane V. Pousa, Luís F. W. Góes, Carlos Augusto Paiva da Silva Martins	Reconfigurable Object Consistency Model.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura	A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Christophe Bobda	Building Up a Course in Reconfigurable Computing.	MSE	2005	DBLP DOI BibTeX RDF
21	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems.	FCCM	2005	DBLP DOI BibTeX RDF
21	Chuan He, Wei Zhao 0001, Mi Lu	Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform.	FCCM	2005	DBLP DOI BibTeX RDF
21	Michael Attig, John W. Lockwood	A Framework for Rule Processing in Reconfigurable Network Systems.	FCCM	2005	DBLP DOI BibTeX RDF
21	Fang Wang, Zeng-Guang Hou, De Xu, Min Tan 0001	An Agent-Based Holonic Architecture for Reconfigurable Manufacturing Systems.	ICNC (3)	2005	DBLP DOI BibTeX RDF
21	Ning Li, Jianchu Kang, Weifeng Lv	A Hybrid Approach for Dynamic Business Process Mining Based On Reconfigurable Nets and Event Types.	ICEBE	2005	DBLP DOI BibTeX RDF
21	Chi-Sheng Shih 0001, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen	Reconfigurable Platform for Content Science Research.	RTCSA	2005	DBLP DOI BibTeX RDF
21	Jih-Ching Chiu, Ren-Bang Lin	FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
21	Siew Kei Lam, Yun Deng, Thambipillai Srikanthan	Morphable Structures for Reconfigurable Instruction Set Processors.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
21	Christiane V. Pousa, Luís F. W. Góes, Carlos Augusto Paiva da Silva Martins	Reconfigurable consistency model for object-based software DSM.	CCGRID	2005	DBLP DOI BibTeX RDF
21	Chris Sullivan, Alex Wilson, Stephen P. G. Chappell	Deterministic Hardware Synthesis for Compiling High-Level Descriptions to Heterogeneous Reconfigurable Architectures.	HICSS	2005	DBLP DOI BibTeX RDF
21	Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis	Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays.	ASAP	2005	DBLP DOI BibTeX RDF
21	Christiane V. Pousa, Luís F. W. Góes, Carlos Augusto Paiva da Silva Martins	Reconfigurable Object Consistency Model for Distributed Shared Memory.	ISPA	2005	DBLP DOI BibTeX RDF
21	Ling Zhuo, Viktor K. Prasanna	High Performance Linear Algebra Operations on Reconfigurable Systems.	SC	2005	DBLP DOI BibTeX RDF
21	John C. Gallagher, Sanjay K. Boddhu, Saranyan A. Vigraham	A Reconfigurable Continuous Time Recurrent Neural Network for Evolvable Hardware Applications.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
21	Lei Li, Zheng Cao, Mingyu Chen 0001, Jianping Fan 0002	A Reconfigurable Optical Interconnect System for DSAG.	PDCAT	2005	DBLP DOI BibTeX RDF
21	João M. P. Cardoso	Self-loop Pipelining and Reconfigurable Dataflow Arrays.	SAMOS	2004	DBLP DOI BibTeX RDF
21	Paul White, K. Kopanski, Hod Lipson	Stochastic Self-reconfigurable Cellular Robotics.	ICRA	2004	DBLP DOI BibTeX RDF
21	Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis	A novel coarse-grain reconfigurable data-path for accelerating DSP kernels.	FPGA	2004	DBLP DOI BibTeX RDF
21	Sashisu Bajracharya, Chang Shu 0003, Kris Gaj, Tarek A. El-Ghazawi	Implementation of elliptic curve cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer.	FPGA	2004	DBLP DOI BibTeX RDF
21	Magesh Sadasivam, Sangjin Hong	Dynamically reconfigurable architecture for high-throughput processing of data centric applications.	FPGA	2004	DBLP DOI BibTeX RDF
21	Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi	A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications.	DATE	2004	DBLP DOI BibTeX RDF
21	Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne	Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors.	DATE	2004	DBLP DOI BibTeX RDF
21	Roberto Pérez, Joaquín Aca, Andrés Valverde T., Horacio Ahuett, Arturo Molina 0001, Carles Riba Romeva	A Modularity Framework for Concurrent Design of Reconfigurable Machine Tools.	CDVE	2004	DBLP DOI BibTeX RDF	Modularity, Reconfigurability, Machine Tool, Concurrent Design
21	Ray C. C. Cheung	A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware.	FPL	2004	DBLP DOI BibTeX RDF