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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 30 occurrences of 20 keywords
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Results
Found 39 publication records. Showing 39 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | |
Panel Summaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 598-599, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IEEE European Test Symposium, IEEE Infrastructure IP Workshop, silicon debug, microelectronics, infrastructure IP |
20 | Yu Huang 0005, Wu-Tung Cheng |
Using embedded infrastructure IP for SOC post-silicon verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 674-677, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA core, infrastructure IP (I-IP), post-silicon verification, transaction-based verification |
16 | Yervant Zorian |
Leveraging Infrastructure IP for SoC Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 3-5, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Yervant Zorian |
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 340-349, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Yervant Zorian |
Embedding infrastructure IP for SOC yield improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 709-712, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
embedded test & repair, semiconductor IP, yield optimization, test resource partitioning |
13 | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
A System-layer Infrastructure for SoC Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 389-404, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SoC diagnosis, Processor and UDL logic self-testing, Memory, Infrastructure-IP |
13 | Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante |
A New Hybrid Fault Detection Technique for Systems-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(2), pp. 185-198, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SoC dependability, transient fault detection, infrastructure IP |
13 | Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green |
Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(3), pp. 232-239, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP |
13 | Nikhil Bansal 0003, Kanishka Lahiri, Anand Raghunathan |
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 513-520, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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13 | C. J. Clark, Mike Ricchetti |
Infrastructure IP for Configuration and Test of Boards and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(3), pp. 78-87, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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13 | Yervant Zorian, Samvel K. Shoukourian |
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(3), pp. 58-66, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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13 | L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot |
Infrastructure IP for Back-End Yield Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1129-1134, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | C. J. Clark |
Tutorial IND2B: Structured Embedded Configuration and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 17, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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10 | Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante |
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 45-56, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Instruction hardening, SET, SEU, Infrastructure IP |
10 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh |
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 1025-1040, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP |
10 | André Ivanov, Giovanni De Micheli |
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(5), pp. 399-403, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
micronetworks, networks on chips, multiprocessor SoCs, on-chip interconnection network, on-chip communication, infrastructure IP |
10 | Praveen Bhojwani, Rabi N. Mahapatra |
An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 867-872, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jui-Jer Huang, Jiun-Lang Huang |
An Infrastructure IP for On-Chip Clock Jitter Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 186-191, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Jason D. Lee, Nikhil Gupta 0004, Praveen Bhojwani, Rabi N. Mahapatra |
An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 184-189, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
test triggering, network on chip, on-line test |
7 | Xinmu Wang, Yu Zheng 0011, Abhishek Basak, Swarup Bhunia |
IIPS: Infrastructure IP for Secure SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 64(8), pp. 2226-2238, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
7 | Chao-Da Huang, Jin-Fu Li 0001, Tsu-Wei Tseng |
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1135-1143, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | R. Chandramouli |
Infrastructure IP design for repair in nanometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(1), pp. 17, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante |
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings, pp. 50-58, 2005, IEEE Computer Society, 0-7695-2282-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 10th European Test Symposium, ETS 2005, Tallinn, Estonia, May 22-25, 2005, pp. 202-207, 2005, IEEE Computer Society, 0-7695-2341-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante |
Hybrid Soft Error Detection by Means of Infrastructure IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 79-88, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Yervant Zorian |
Guest Editor's Introduction: Advances in Infrastructure IP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(3), pp. 49-, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
7 | |
Guest Editor's Introduction: What is Infrastructure IP? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(3), pp. 5-7, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
6 | Yervant Zorian, Juan Antonio Carballo |
T1: Design for Manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
6 | R. Chandramouli |
Managing Test and Repair of Embedded Memory Subsystem in SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 452, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
6 | N. Derhacobian, Valery A. Vardanian, Yervant Zorian |
Embedded Memory Reliability: The SER Challenge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 104-110, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
6 | Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda |
Exploiting an I-IP for In-Field SOC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 404-412, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
6 | Eric Dupont, Michael Nicolaidis |
Robustness IPs for Reliability and Security of SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 357-364, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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3 | Jason D. Lee, Rabi N. Mahapatra |
In-field NoC-based SoC testing with distributed test vector storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 206-211, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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3 | Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda |
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1158-1163, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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3 | Letícia Maria Veiras Bolzani, Paolo Bernardi, Matteo Sonza Reorda |
An optimized hybrid approach to provide fault detection and correction in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 342-347, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault correction, SoCs, fault detection, hybrid approach |
3 | Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda |
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 412-417, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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3 | Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero |
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 37-41, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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3 | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 55-62, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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3 | Miron Abramovici, Charles E. Stroud, John Marty Emmert |
Using embedded FPGAs for SoC yield improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 713-724, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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