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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 26884 occurrences of 7514 keywords
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Results
Found 51597 publication records. Showing 51597 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
48 | Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera |
Radix-4 Vectoring Cordic Algorithm And Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 55-64, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
radix-4 vectoring CORDIC algorithm, radix-4 vectoring CORDIC architectures, vectoring mode, microrotations, zero skipping technique, recursive architectures, matrix triangularization, rotation angle, computational complexity, complexity, parallel architectures, singular value decomposition, SVD, signal processing, digital arithmetic, digital arithmetic, matrix algebra, pipelined architectures |
42 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 172-182, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Richard T. Bechtold |
Diagnostic Software Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESPRIT ARES Workshop ![In: Development and Evolution of Software Architectures for Product Families, Second International ESPRIT ARES Workshop, Las Palmas de Gran Canaria, Spain, February 26-27, 1998, Proceedings, pp. 143-147, 1998, Springer, 3-540-64916-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Diagnostic Software Architectures, Error Management, Software Families, Embedded Systems, Software Architectures |
38 | Roger Olmstead |
Compilers and parallel architectures (abstract only): sequential to parallel mapping strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the 15th ACM Annual Conference on Computer Science, St. Louis, Missouri, USA, February 16-19, 1987, pp. 424, 1987, ACM, 0-89791-218-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
38 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Synthesis System For Bus-Based Wavefront Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 274-283, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations |
38 | Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary |
Compiler Algorithms for Optimizing Locality and Parallelism on Shared and Distributed Memory Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 236-, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
storage layout, SUN SPARCstation 5, IBM SP-2, SGI Challenge, Convex Exemplar, parallel architectures, parallel architectures, optimizing compilers, interprocessor communication, cache performance, distributed memory machines, shared memory machines, loop nests, data decomposition, compiler algorithms |
37 | Yan Liu 0001, Ian Gorton, Len Bass, Cuong Hoang, Suhail Abanmi |
MEMS: A Method for Evaluating Middleware Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QoSA ![In: Quality of Software Architectures, Second International Conference on Quality of Software Architectures, QoSA 2006, Västerås, Sweden, June 27-29, 2006 Revised Papers, pp. 9-26, 2006, Springer, 3-540-48819-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Carl Ebeling, Darren C. Cronquist, Paul Franklin |
Configurable computing: the catalyst for high-performance architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 364-373, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
high-performance architectures, cost-performance, application-specific computation pipelines, static configuration, FPGAs, computational complexity, computer architectures, configurable computing, dynamic control, RaPiD, application-specific hardware |
35 | Flávio Oquendo |
pi-ADL: an Architecture Description Language based on the higher-order typed pi-calculus for specifying dynamic and mobile software architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGSOFT Softw. Eng. Notes ![In: ACM SIGSOFT Softw. Eng. Notes 29(3), pp. 1-14, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
specification languages, Architecture Description Languages, ?-calculus, dynamic architectures, mobile architectures |
34 | D. K. Arvind 0001 |
Distributed simulation of parallel VLSI architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 285-298, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
34 | Patrice Quinton, Yves Robert |
Algorithms and Parallel VLSI Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 1-10, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
34 | Marc Moonen |
Algorithms and architectures for recursive total least squares estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 39-46, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
32 | Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas |
The Augmint multiprocessor simulation toolkit for Intel x86 architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 486-490, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Augmint multiprocessor simulation toolkit, Intel x86 architectures, publicly available simulation tools, instruction mix, memory reference patterns, CISC architectures, execution driven multiprocessor simulation toolkit, m4 macro extended C, C++ applications, SPLASH-2 benchmark suites, thread based programming model, shared global address space, private stack space, simulator interface, MINT simulation toolkit, x8d based uniprocessor systems, multiprocessing systems, trace driven simulation, architecture simulators, uniprocessors |
32 | James D. Allen, David E. Schimmel |
The impact of pipelining on SIMD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 380-387, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
massively parallel SIMD architectures, stall penalties, reduction operations, Scheduling mechanisms, area costs, scheduling, parallel architectures, pipelining, program compilers, pipeline processing, performance improvement, SIMD architectures, instruction delivery |
31 | Krishna M. Kavi, Roberto Giorgi, Joseph Arul |
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(8), pp. 834-846, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
superscalar, Thread Level Parallelism, Multithreaded architectures, decoupled architectures, dataflow architectures |
30 | Joanna Bryson, Lynn Andrea Stein |
Modularity and Specialized Learning: Mapping between Agent Architectures and Brain Organization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Emergent Neural Computational Architectures Based on Neuroscience ![In: Emergent Neural Computational Architectures Based on Neuroscience - Towards Neuroscience-Inspired Computing, pp. 98-113, 2001, Springer, 3-540-42363-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Structural and Temporal Modularity, Complete Autonomous Agents, Behavior-Based AI, Brain Organization, Action Selection and Synchronization, Perceptual, Episodic and Semantic Memory, Spatial |
30 | Samuil Angelov, Paul W. P. J. Grefen, Danny Greefhorst |
A classification of software reference architectures: Analyzing their success and effectiveness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WICSA/ECSA ![In: Joint Working IEEE/IFIP Conference on Software Architecture 2009 and European Conference on Software Architecture 2009, WICSA/ECSA 2009, Cambridge, UK, 14-17 September 2009, pp. 141-150, 2009, IEEE Computer Society, 978-1-4244-4984-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Ah Chung Tsoi |
Recurrent Neural Network Architectures: An Overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Summer School on Neural Networks ![In: Adaptive Processing of Sequences and Data Structures, International Summer School on Neural Networks, `E.R. Caianiello`, Vietri sul Mare, Salerno, Italy, September 6-13, 1997, Tutorial Lectures, pp. 1-26, 1997, Springer, 3-540-64341-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | John Hannan |
Operational Semantics-Directed Compilers and Machine Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 16(4), pp. 1215-1247, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
pass separation, semantics-based compilation, abstract machines |
30 | Philip Heidelberger, M. Seetha Lakshmi |
A Performance Comparison of Multi-Micro and Mainframe Database Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Banff, Alberta, Canada, May 11-14, 1987, pp. 5-6, 1987, ACM, 0-89791-225-X. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
30 | JongSoo Park, William J. Dally |
Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, Thira, Santorini, Greece, June 13-15, 2010, pp. 1-10, 2010, ACM, 978-1-4503-0079-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
compiler and tools for concurrent programming, green computing and power-efficient architectures, multi-core architectures, stream programming |
30 | Marco Ferretti |
Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 249-, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing |
30 | Roberto R. Osorio, Javier D. Bruguera |
New arithmetic coder/decoder architectures based on pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 106-115, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
arithmetic coder/decoder architectures, arithmetic encoding, arithmetic decoding, multilevel images, cycle length, VLSI, pipelining, VLSI architectures |
30 | Jing-Chiou Liou, Michael A. Palis |
CASS: an efficient task management system for distributed memory architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 289-295, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
CASS, granularity optimization, parallel algorithm, parallelism, compiler, parallel architectures, operating system, task scheduling, task management, distributed memory architectures |
30 | Lukasz Strozek, David M. Brooks |
Energy- and area-efficient architectures through application clustering and architectural heterogeneity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(1), pp. 4:1-4:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Efficient custom architectures, heterogeneous ISA processors |
30 | Jaehong Park, Ravi S. Sandhu, J. Schifalacqua |
Security Architectures for Controlled Digital Information Dissemination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 224-, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
controlled digital information dissemination, application-level security, use control, control set, distribution style, cryptography, virtual machine, watermarking, security of data, business data processing, information dissemination, security architectures, business, copy protection |
30 | Chandra Shekhar 0001, Raj Singh, A. S. Mandal, S. C. Bose, Ravi Saini, Pramod Tanwar |
Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 915-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Jesper Berthing, Thomas Maier |
A Taxonomy for Modelling Safety Related Architectures in Compliance with Functional Safety Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFECOMP ![In: Computer Safety, Reliability, and Security, 26th International Conference, SAFECOMP 2007, Nuremberg, Germany, September 18-21, 2007., pp. 505-517, 2007, Springer, 978-3-540-75100-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dependable architectures, safety related architectures, IEC61508 |
29 | Danilo Ardagna, Chiara Francalanci |
A cost-oriented methodology for the design of web based IT architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), March 10-14, 2002, Madrid, Spain, pp. 1127-1133, 2002, ACM, 1-58113-445-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
IT architectures, web architectures, cost minimization |
29 | Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin |
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(10), pp. 1121-1128, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
area time trade-offs, micro-grain VLSI array architectures, massively parallel control-flow architectures, associative memory architecture, Mux-based SIMD architecture, systolic MIMD/MISD computation, data-flow requirements, performance evaluation, performance, VLSI, parallel architectures, FFT, matrix multiplication, RAMs |
29 | Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault |
Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(9), pp. 1105-1120, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
photonic architectures, optical structures, processor interconnection, single-hop, optical fiber communication, parallel architectures, discrete-event simulation, discrete event simulation, analytic models, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, hierarchical, parallel computer architecture, hierarchical architectures |
28 | Wolfgang Karl |
Some Design Aspects for VLIW Architectures Exploiting Fine - Grained Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE ![In: PARLE '93, Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany, June 14-17, 1993, Proceedings, pp. 582-599, 1993, Springer, 3-540-56891-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Yahya Jan, Lech Józwiak |
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 24-35, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC |
28 | Yahya Jan, Lech Józwiak |
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 342-348, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC |
28 | Claudia Canali, Sara Casolari, Riccardo Lancellotti |
Architectures for scalable and flexible Web personalization services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAA-IDEA ![In: First International Workshop on Advanced Architectures and Algorithms for Internet Delivery and Applications, AAA-IDEA 2005, Orlando, Florida, USA, June 15, 2005, pp. 50-57, 2005, IEEE Computer Society, 0-7695-2525-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Web content adaptation, High performance architectures, Web content delivery |
28 | Alfred Zimmermann, Rainer Schmidt 0001, Kurt Sandkuhl, Eman El-Sheikh, Dierk Jugel, Christian M. Schweda, Michael Möhring, Matthias Wißotzki, Birger Lantow |
Leveraging Analytics for Digital Transformation of Enterprise Services and Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures ![In: Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures, pp. 91-112, 2016, 978-3-319-40562-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Michael Gebhart, Pascal Giessler, Sebastian Abeck |
Flexible and Maintainable Service-Oriented Architectures with Resource-Oriented Web Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures ![In: Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures, pp. 23-39, 2016, 978-3-319-40562-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Eman El-Sheikh, Alfred Zimmermann, Lakhmi C. Jain |
Evolution of Service-Oriented and Enterprise Architectures: An Introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures ![In: Emerging Trends in the Evolution of Service-Oriented and Enterprise Architectures, pp. 1-3, 2016, 978-3-319-40562-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Iván Contreras, José Ignacio Hidalgo, Laura Núñez-Letamendia, Yiyi Jiang |
Parallel Architectures for Improving the Performance of a GA Based Trading System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Architectures and Bioinspired Algorithms ![In: Parallel Architectures and Bioinspired Algorithms, pp. 189-218, 2012, Springer, 978-3-642-28788-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Marianne J. Jantz, Prasad A. Kulkarni |
Understand and categorize dynamically dead instructions for contemporary architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 16th Workshop on Interaction between Compilers and Computer Architectures, INTERACT 2012, New Orleans, LA, USA, February 25, 2012, pp. 25-32, 2012, IEEE Computer Society, 978-1-4673-2613-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Ahmed Al-Maashri, Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Narayanan Vijaykrishnan |
Influence of Stacked 3D Memory/Cache Architectures on GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 249-271, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Shan Yan, Bill Lin 0001 |
Design of Application-Specific 3D Networks-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 167-191, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Jon G. Hall, John Grundy 0001, Ivan Mistrík, Patricia Lago, Paris Avgeriou |
Introduction: Relating Requirements and Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Relating Software Requirements and Architectures ![In: Relating Software Requirements and Architectures., pp. 1-9, 2011, Springer, 978-3-642-21000-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Luciano Baresi, Liliana Pasquale |
Adaptation Goals for Adaptive Service-Oriented Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Relating Software Requirements and Architectures ![In: Relating Software Requirements and Architectures., pp. 161-181, 2011, Springer, 978-3-642-21000-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Carlos Kavka, Luka Onesti, Enrico Rigoni, Alessandro Turco, Sara Bocchio, Fabrizio Castro, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Giovanni Mariani, Dongrui Fan, Hao Zhang 0009, Shibin Tang |
Design Space Exploration of Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures ![In: Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, The MULTICUBE Approach., pp. 171-188, 2011, Springer, 978-1-4419-8836-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Peter M. Athanas, Jürgen Becker 0001, Jürgen Teich, Ingrid Verbauwhede |
10281 Abstracts Collection - Dynamically Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
28 | Peter M. Athanas, Jürgen Becker 0001, Jürgen Teich, Ingrid Verbauwhede |
10281 Summary - Dynamically Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
28 | Matthias Hanke, Tim Kranich, Mladen Berekovic, Yannis Papaefstathiou |
Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
28 | Karl Cheng-Heng Fua, Ian Horswill, Andrew Ortony, William Revelle |
Reinforcement Sensitivity Theory and Cognitive Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Fall Symposium: Biologically Inspired Cognitive Architectures ![In: Biologically Inspired Cognitive Architectures, Papers from the 2009 AAAI Fall Symposium, Arlington, Virginia, USA, November 5-7, 2009, 2009, AAAI. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
28 | Matthew Klenk |
Transfer as a Benchmark for Multi-Representational Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Fall Symposium: Multi-Representational Architectures for Human-Level Intelligence ![In: Multi-Representational Architectures for Human-Level Intelligence, Papers from the 2009 AAAI Fall Symposium, Arlington, Virginia, USA, November 5-7, 2009, 2009, AAAI. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
28 | Steven Brian Morphet |
An Engineering View of Cognitive Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Fall Symposium: Biologically Inspired Cognitive Architectures ![In: Biologically Inspired Cognitive Architectures, Papers from the 2009 AAAI Fall Symposium, Arlington, Virginia, USA, November 5-7, 2009, 2009, AAAI. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
28 | Gary Berg-Cross |
Emergently Developed Cognitive Architectures: Testing by Developmental Robotics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Fall Symposium: Biologically Inspired Cognitive Architectures ![In: Biologically Inspired Cognitive Architectures, Papers from the 2009 AAAI Fall Symposium, Arlington, Virginia, USA, November 5-7, 2009, 2009, AAAI. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
28 | Annie A. M. Cuyt, Walter Krämer, Wolfram Luther, Peter W. Markstein |
08021 Summary - Numerical Validation in Current Hardware Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Numerical Validation in Current Hardware Architectures ![In: Numerical Validation in Current Hardware Architectures, 6.1. - 11.1.2008, 2008, Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
28 | Wolfram Luther, Annie A. M. Cuyt, Walter Krämer, Peter W. Markstein |
08021 Abstracts Collection - Numerical Validation in Current Hardware Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Numerical Validation in Current Hardware Architectures ![In: Numerical Validation in Current Hardware Architectures, 6.1. - 11.1.2008, 2008, Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
28 | Rodrigo Ventura 0001 |
Action and Adaptation: Lessons from Neurobiology and Challenges for Robot Cognitive Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Fall Symposium: Biologically Inspired Cognitive Architectures ![In: Biologically Inspired Cognitive Architectures, Papers from the 2008 AAAI Fall Symposium, Arlington, Virginia, USA, November 7-9, 2008, pp. 189-194, 2008, AAAI. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
28 | Stephen Grossberg |
Towards Self-Organizing Autonomous Brain-Inspired Cognitive Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Fall Symposium: Biologically Inspired Cognitive Architectures ![In: Biologically Inspired Cognitive Architectures, Papers from the 2008 AAAI Fall Symposium, Arlington, Virginia, USA, November 7-9, 2008, pp. 78-79, 2008, AAAI. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
28 | Claudius Gros, Gregor Kaczor |
Evolving Complete Cognitive Architectures: The Role of Neural Competition and Diffusive Emotional Control for Learning and Emergent Cognitive Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Fall Symposium: Biologically Inspired Cognitive Architectures ![In: Biologically Inspired Cognitive Architectures, Papers from the 2008 AAAI Fall Symposium, Arlington, Virginia, USA, November 7-9, 2008, pp. 77, 2008, AAAI. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
28 | Jürgen Nehmer, Thomas Kleinberger |
07462 Summary -- Assisted Living Systems - Models, Architectures and Engineering Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Assisted Living Systems - Models, Architectures and Engineering Approaches ![In: Assisted Living Systems - Models, Architectures and Engineering Approaches, 14.11. - 17.11.2007, 2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
28 | Arthur I. Karshmer, Jürgen Nehmer, Hartmut Raffler, Gerhard Tröster |
07462 Abstracts Collection -- Assisted Living Systems - Models, Architectures and Engineering Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Assisted Living Systems - Models, Architectures and Engineering Approaches ![In: Assisted Living Systems - Models, Architectures and Engineering Approaches, 14.11. - 17.11.2007, 2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
28 | Mihai Barbuceanu, Rune Teigen |
Higher Level Integration by Multi-Agent Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook on Architectures of Information Systems ![In: Handbook on Architectures of Information Systems, pp. 855-886, 2006, Springer, 978-3-540-25472-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Rainer Buchty |
Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
28 | Frank Leymann, Wolfgang Reisig, Satish R. Thatte, Wil M. P. van der Aalst |
06291 Abstracts Collection -- The Role of Business Processes in Service-Oriented Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
The Role of Business Processes in Service Oriented Architectures ![In: The Role of Business Processes in Service Oriented Architectures, 16.07. - 21.07.2006, 2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
28 | Jürgen Becker 0001, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas |
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
28 | Jürgen Becker 0001, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas |
06141 Executive Summary -- Dynamically Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
28 | Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, Paul M. Heysters |
Efficient architectures for streaming applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dynamically Reconfigurable Architectures ![In: Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
28 | Erik R. Altman, James C. Dehnert, Christoph W. Kessler, Jens Knoop |
05101 Executive Summary - Scheduling for Parallel Architectures: Theory, Applications, Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scheduling for Parallel Architectures ![In: Scheduling for Parallel Architectures: Theory, Applications, Challenges, 2005, Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
28 | Erik R. Altman, James C. Dehnert, Christoph W. Kessler, Jens Knoop |
05101 Abstracts Collection - Scheduling for Parallel Architectures: Theory, Applications, Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scheduling for Parallel Architectures ![In: Scheduling for Parallel Architectures: Theory, Applications, Challenges, 2005, Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
28 | Carlos Molina, Antonio González 0001, Jordi Tubella |
Compiler analysis for trace-level speculative multithreaded architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 9th Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT-9 2005, San Francisco, California, USA, February 13, 2005, pp. 2-10, 2005, IEEE Computer Society, 0-7695-2321-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Michael J. Wooldridge, Nicholas R. Jennings |
Agent Theories, Architectures, and Languages: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECAI Workshop on Agent Theories, Architectures, and Languages ![In: Intelligent Agents, ECAI-94 Workshop on Agent Theories, Architectures, and Languages, Amsterdam, The Netherlands, August 8-9, 1994, Proceedings, pp. 1-39, 1994, Springer, 3-540-58855-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
28 | Jörg P. Müller, Markus Pischel, Michael Thiel |
Modelling Reactive Behaviour in Vertically Layered Agent Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECAI Workshop on Agent Theories, Architectures, and Languages ![In: Intelligent Agents, ECAI-94 Workshop on Agent Theories, Architectures, and Languages, Amsterdam, The Netherlands, August 8-9, 1994, Proceedings, pp. 261-276, 1994, Springer, 3-540-58855-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
28 | Jack J. Stiffler |
Fault Tolerant Architectures - Past, Present, and (?) Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware and Software Architectures for Fault Tolerance ![In: Hardware and Software Architectures for Fault Tolerance, Experiences and Perspecives [revised papers from a workshop at Le Mont Saint Michel, France, June 1993], pp. 117-121, 1993, Springer, 3-540-57767-X. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | David A. Berson, Rajiv Gupta 0001, Mary Lou Soffa |
URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism ![In: Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, PACT 1993, Orlando, Florida, USA, January 20-22, 1993, pp. 243-254, 1993, North-Holland, 0-444-88464-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
28 | G. Menez, Michel Auguin, Fernand Boéri, C. Carrière |
Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism ![In: Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, PACT 1993, Orlando, Florida, USA, January 20-22, 1993, pp. 217-228, 1993, North-Holland, 0-444-88464-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
28 | Stephan Murer, Philipp Färber |
Code Generation for Multi-Threaded Architectures from Dataflow Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism ![In: Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, PACT 1993, Orlando, Florida, USA, January 20-22, 1993, pp. 77-90, 1993, North-Holland, 0-444-88464-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
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28 | Henning Spruth, Frank M. Johannes |
Architectures for Parallel Slicing Enumeration in VLSI Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Computer Architectures ![In: Parallel Computer Architectures: Theory, Hardware, Software, Applications, pp. 219-233, 1993, Springer, 3-540-57307-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Patrice Quinton, Yves Robert (eds.) |
Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991 ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![Elsevier, 0-444-89153-6 The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
28 | Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes |
Generalized cycle shrinking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 131-144, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | Jingling Xue, Christian Lengauer |
Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 181-186, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Selim G. Akl, John M. Calvert, Ivan Stojmenovic |
Systolic generation of derangements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 59-70, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | John G. McWhirter, Ian K. Proudler |
Orthogonal lattice algorithms for adaptive filtering and beamforming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 11-24, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | M. Van Swaalj, Francky Catthoor, Hugo De Man |
Signal analysis and signal transformations for ASIC regular array architecture synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 223-232, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Sanjay V. Rajopadhye |
An improved systolic algorithm for the algebraic path problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 187-198, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Mokhtar Aboelaze, De-Lei Lee, Benjamin W. Wah |
A programmable VLSI array with constant I/O pins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 205-210, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Catherine Dezan, Hervé Le Verge, Patrice Quinton, Yannick Saouter |
The Alpha du Centaur environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 325-334, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Tanguy Risset |
Linear systolic arrays for matrix multiplication: comparisons of existing synthesis methods and new results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 163-174, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Frédéric Rocheteau, Nicolas Halbwachs |
POLLUS: A LUSTRE based hardware design environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 335-346, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Alle-Jan van der Veen, Patrick M. Dewilde |
Time-varying system theory for computational networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 103-130, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Frédéric Dufaux, Murat Kunt |
Matrix Multiplication on an associative string processor: application to image compression by Gabor expansion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 305-310, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Rumen Andonov, Frédéric Gruau |
A 2D toroidal systolic array for the knapsack problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 71-78, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Ravi Varadarajan, Bhavani Ravichandran |
Refinement based algorithm mapping techniques for linear systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 175-180, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch |
Synthesis of intermediate memories for the data supply to processor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 365-370, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | Alain Darte |
Two heuristics for task scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 383-, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis |
Direct mapping of nested loops on piecewise regular processor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 145-150, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | Vincent Van Dongen |
From systolic to periodic array design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 151-162, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | Paul Le Guernic |
The SIGNAL programming environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 347-358, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | Frank K. H. A. Dehne, Andrew Rau-Chaplin |
Parallel algorithms for color image quantization on hypercubes and meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 91-96, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
28 | Uwe Vehlies |
The derivation of dependence graphs from PASCAL programs for array processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 371-376, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Mohammad Shakeel Laghari, Farzin Deravi |
Comparison of scheduling techniques for the parallel implementation of the Hough transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 377-382, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Francky Catthoor, M. Van Swaalj, Jan Rosseel, Hugo De Man |
Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 211-222, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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28 | Gur Saran Adhar, Shietung Peng |
Parallel algorithms for finding connected, independent and total domination in interval graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 85-90, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
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