Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link
12	Daniel Hansson	Automatic Bug Fixing.	MTV	2015	DBLP DOI BibTeX RDF
12	Mohamed A. Salem, Kerstin I. Eder	Novel MC/DC Coverage Test Sets Generation Algorithm, and MC/DC Design Fault Detection Strength Insights.	MTV	2015	DBLP DOI BibTeX RDF
12	Rico Angell, Ben Oztalay, Andrew DeOrio	A Topological Approach to Hardware Bug Triage.	MTV	2015	DBLP DOI BibTeX RDF
12	James D. Warnock, Yuen H. Chan, Hubert Harrer, Sean M. Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey A. Zitz, Adam Jatkowski, Gerald Strevig, Ayan Datta, Anne Gattiker, Aditya Bansal, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, David L. Rude, Leon J. Sigal, Thomas Strach, Howard H. Smith, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb	Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
12	Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente	Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor.	IEEE Trans. Reliab.	2014	DBLP DOI BibTeX RDF
12	Zao Liu, Sheldon X.-D. Tan, Hai Wang 0002, Yingbo Hua, Ashish Gupta 0007	Compact thermal modeling for packaged microprocessor design with practical power maps.	Integr.	2014	DBLP DOI BibTeX RDF
12	Nektarios Georgios Tsoutsos, Michail Maniatakos	Fabrication Attacks: Zero-Overhead Malicious Modifications Enabling Modern Microprocessor Privilege Escalation.	IEEE Trans. Emerg. Top. Comput.	2014	DBLP DOI BibTeX RDF
12	Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata	AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model.	IEICE Trans. Electron.	2014	DBLP DOI BibTeX RDF
12	Paolo Bernardi, Lyl Mercedes Ciganda, Ernesto Sánchez 0001, Matteo Sonza Reorda	MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
12	Fabian Oboril, Mehdi Baradaran Tahoori	Aging-Aware Design of Microprocessor Instruction Pipelines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
12	Hwajeong Seo, Jihyun Kim 0005, Jongseok Choi, Taehwan Park, Zhe Liu 0001, Howon Kim 0001	Small Private Key MQPKS on an Embedded Microprocessor.	Sensors	2014	DBLP DOI BibTeX RDF
12	Frank Liu 0001, Ben R. Hodges	Applying microprocessor analysis methods to river network modelling.	Environ. Model. Softw.	2014	DBLP DOI BibTeX RDF
12	Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri	Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.	DDECS	2014	DBLP DOI BibTeX RDF
12	Uwe Brinkschulte, Daniel Lohn, Michael Bauer	Design and Evaluation of an Energy-Saving Real-Time Microprocessor.	ISORC	2014	DBLP DOI BibTeX RDF
12		15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014	MTV	2014	DBLP BibTeX RDF
12	Chen-Bo Hsu, James B. Kuo	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS.	MWSCAS	2014	DBLP DOI BibTeX RDF
12	K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle	Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
12	Waleed Dweik, Murali Annavaram, Michel Dubois 0001	Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures.	DATE	2014	DBLP DOI BibTeX RDF
12	Cong Wang, Naehyuck Chang, Younghyun Kim 0001, Sangyoung Park, Yongpan Liu, Hyung Gyu Lee, Rong Luo, Huazhong Yang	Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor.	ASP-DAC	2014	DBLP DOI BibTeX RDF
12	Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo	Co-simulation framework for streamlining microprocessor development on standard ASIC design flow.	ASP-DAC	2014	DBLP DOI BibTeX RDF
12	Daxin Luo, Yaoda Liu, Xiaoying Liu, Bin Zhang, Gang Li, Qi Liao, Qinfen Hao, Zhulin Wei	Optical Interconnects between Microprocessor and Memories.	HPCC/CSS/ICESS	2014	DBLP DOI BibTeX RDF
12	Mohamed Amine Boussadi, Thierry Tixier, Alexis Landrault, Jean-Pierre Dérutin	HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithms.	ReCoSoC	2014	DBLP DOI BibTeX RDF
12	K. Chibani, Salma Bergaoui, Michele Portolan, Régis Leveugle	Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options.	ICECS	2014	DBLP DOI BibTeX RDF
12	Brian Campbell 0001, Ian Stark	Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation.	FMICS	2014	DBLP DOI BibTeX RDF
12	Hantao Huang, Sai Manoj Pudukotai Dinakarrao, Dongjun Xu, Hao Yu 0001, Zhigang Hao	Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication.	ICCAD	2014	DBLP DOI BibTeX RDF
12	Robert A. Groves, Phillip J. Restle, Alan J. Drake, David Shan, Michael G. R. Thomson	Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor.	CICC	2014	DBLP DOI BibTeX RDF
12	Marco Aiello 0002, Antonio Bruscino, Antonio Di Marzo, Michele Paragliola	nSHIELD-Gateway - A Hybrid FPGA-Microprocessor based Architecture to Foster the Interconnection of Embedded Systems.	PECCS	2014	DBLP DOI BibTeX RDF
12	Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger	5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor.	ISSCC	2014	DBLP DOI BibTeX RDF
12	Kris Myny, Steve Smout, Maarten Rockele, Ajay Bhoolokam, Tung Huei Ke, Soeren Steudel, Koji Obata, B. M. Marín-Santibáñez, Duy-Vu Pham, Arne Hoppe, Aashini Gulati, F. Rodríguez González, Brian Cobb, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans	30.1 8b Thin-film microprocessor using a hybrid oxide-organic complementary technology with inkjet-printed P2ROM memory.	ISSCC	2014	DBLP DOI BibTeX RDF
12	Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich	5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor.	ISSCC	2014	DBLP DOI BibTeX RDF
12	Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich	5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor.	ISSCC	2014	DBLP DOI BibTeX RDF
12	Mostafa Mohamed, Patrick Sebastian, Lo Hai Hiung, Shawn Tan Ser Ngiap	Threading optimization of the AEMB microprocessor.	ICCSCE	2014	DBLP DOI BibTeX RDF
12	Jared Davis, Anna Slobodová, Sol Swords	Microcode Verification - Another Piece of the Microprocessor Verification Puzzle.	ITP	2014	DBLP DOI BibTeX RDF
12	Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus	Laboratory framework TEAM for investigating the dependability issues of microprocessor systems.	EWME	2014	DBLP DOI BibTeX RDF
12	Dirk Jansen, Benjamin Dusch	Every student makes his own microprocessor.	EWME	2014	DBLP DOI BibTeX RDF
12	Manolis Kaliorakis, Mihalis Psarakis, Nikos Foutris, Dimitris Gizopoulos	Accelerated online error detection in many-core microprocessor architectures.	VTS	2014	DBLP DOI BibTeX RDF
12	Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, Ching-Te Chiu	Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
12	Chen-Bo Hsu, James B. Kuo	MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits.	ISIC	2014	DBLP DOI BibTeX RDF
12	Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura	A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator.	A-SSCC	2014	DBLP DOI BibTeX RDF
12	Zdenek Prikryl	Fast Simulation of Pipeline in ASIP Simulators.	MTV	2014	DBLP DOI BibTeX RDF
12	Deepak Venkatesan, Pradeep Nagarajan	A Case Study of Multiprocessor Bugs Found Using RIS Generators and Memory Usage Techniques.	MTV	2014	DBLP DOI BibTeX RDF
12	Michele Lora, Francesco Martinelli, Franco Fummi	Hardware Synthesis from Software-Oriented UML Descriptions.	MTV	2014	DBLP DOI BibTeX RDF
12	Michael Mefenza, Franck Yonga, Christophe Bobda	Automatic UVM Environment Generation for Assertion-Based and Functional Verification of SystemC Designs.	MTV	2014	DBLP DOI BibTeX RDF
12	Mohamed O. Kayed, Mohamed Abdelsalam, Rafik Guindi	A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML.	MTV	2014	DBLP DOI BibTeX RDF
12	Weihua Han	Improve the Verification Productivity: Some Best Practices from SoC and Processor Projects.	MTV	2014	DBLP DOI BibTeX RDF
12	John Hudson, Gunaranjan Kurucheti	A Configurable Random Instruction Sequence (RIS) Tool for Memory Coherence in Multi-processor Systems.	MTV	2014	DBLP DOI BibTeX RDF
12	Daniel Hansson	Continuous Linting with Automatic Debug.	MTV	2014	DBLP DOI BibTeX RDF
12	Parikshit Pritam Dhodapkar	Synthesizable Memory Models for Virtual Prototyping.	MTV	2014	DBLP DOI BibTeX RDF
12	Ganesh Venkatakrishnan, Naresh Kumar Kadali	'Dump What You Need' - A Coverage Methodology to Accelerate SoC Verification.	MTV	2014	DBLP DOI BibTeX RDF
12	Somnath Banerjee 0003, Tushar Gupta	Optimized Simulation Acceleration with Partial Testbench Evaluation.	MTV	2014	DBLP DOI BibTeX RDF
12	Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky	System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation.	MTV	2014	DBLP DOI BibTeX RDF
12	Nitin Gupta, Chethan Harakchand	Embracing the FPGA Challenge for Processor Design Verification.	MTV	2014	DBLP DOI BibTeX RDF
12	Peter-Michael Seidel	Directed Test Case Generation for x86 Instruction Decoding.	MTV	2014	DBLP DOI BibTeX RDF
12	Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey	Mutation Based Feature Localization.	MTV	2014	DBLP DOI BibTeX RDF
12	Lukás Charvát, Ales Smrcka, Tomás Vojnar	Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors.	MTV	2014	DBLP DOI BibTeX RDF
12	Shajid Thiruvathodi, Deepak Yeggina	A Random Instruction Sequence Generator for ARM Based Systems.	MTV	2014	DBLP DOI BibTeX RDF
12	Andrea Höller, Gerhard Schonfelder, Nermin Kajtazovic, Tobias Rauter, Christian Kreiner	FIES: A Fault Injection Framework for the Evaluation of Self-Tests for COTS-Based Safety-Critical Systems.	MTV	2014	DBLP DOI BibTeX RDF
12	Maneesh Kumar Pandey, Shwetank Shekhar, Amit Sinha, Arun Mishra	An FPGA Based Ecosystem for USBPHY Validation.	MTV	2014	DBLP DOI BibTeX RDF
12	Peter-Michael Seidel	A Case for Multi-level Combination of Theorem Proving and Model Checking Tools.	MTV	2014	DBLP DOI BibTeX RDF
12	Mrugesh Walimbe	JTAG-AXI Debug IP with Performance Meter Mode.	MTV	2014	DBLP DOI BibTeX RDF
12	Visvesh S. Sathe 0001, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger	Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
12	Ching-Hwa Cheng	Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor.	VLSI Design	2013	DBLP DOI BibTeX RDF
12	C. Kevin Shum, Fadi Busaba, Christian Jacobi 0002	IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor.	IEEE Micro	2013	DBLP DOI BibTeX RDF
12	Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni	Nanomagnetic Logic Microprocessor: Hierarchical Power Model.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
12	Zbigniew Stachniak	This Is Not a Computer: Negotiating the Microprocessor.	IEEE Ann. Hist. Comput.	2013	DBLP DOI BibTeX RDF
12	Rupesh S. Shelar, Marek Patyra	Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
12	Tianshi Chen 0002, Yunji Chen, Qi Guo 0001, Zhi-Hua Zhou, Ling Li 0001, Zhiwei Xu 0002	Effective and efficient microprocessor design space exploration using unlabeled design configurations.	ACM Trans. Intell. Syst. Technol.	2013	DBLP DOI BibTeX RDF
12	Maximilien Breughe, Lieven Eeckhout	Selecting representative benchmark inputs for exploring microprocessor design spaces.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
12	Angeliki Kritikakou, Francky Catthoor, George Athanasiou, Vasilios I. Kelefouras, Costas E. Goutis	Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
12	L. N. Stepanova, S. I. Kabanov, S. A. Bekher, M. S. Nikitenko	Microprocessor multi-channel strain-gauge systems for dynamic tests of structures.	Autom. Remote. Control.	2013	DBLP DOI BibTeX RDF
12		Microprocessor architectures follow markets and silicon.	Commun. ACM	2013	DBLP DOI BibTeX RDF
12	Ana Aizcorbe, Samuel Kortum, Unni Pillai	The value of microprocessor designs.	Commun. ACM	2013	DBLP DOI BibTeX RDF
12	Chang-Chih Chen, Fahad Ahmed, Linda Milor	Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
12	Adam Golda, Andrzej Kos	Optimum control of microprocessor throughput under thermal and energy saving constraints.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
12	David P. Montminy, Rusty O. Baldwin, Michael A. Temple, Mark E. Oxley	Differential Electromagnetic Attacks on a 32-bit Microprocessor Using Software Defined Radios.	IEEE Trans. Inf. Forensics Secur.	2013	DBLP DOI BibTeX RDF
12	Naga Pavan Kumar Gorti, Arun K. Somani	Reliability aware dynamic voltage and frequency scaling for improved microprocessor lifetime.	ACM SIGOPS Oper. Syst. Rev.	2013	DBLP DOI BibTeX RDF
12	Diego González 0002, Guillermo Botella, Carlos García 0001, Manuel Prieto 0001, Francisco Tirado	Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor.	EURASIP J. Adv. Signal Process.	2013	DBLP DOI BibTeX RDF
12	Stephen Wright, Kerstin Eder	Experience of Deploying Event-B in Industrial Microprocessor Development.	Industrial Deployment of System Engineering Methods	2013	DBLP DOI BibTeX RDF
12		14th International Workshop on Microprocessor Test and Verification, MTV 2013, Austin, TX, USA, December 11-13, 2013	MTV	2013	DBLP BibTeX RDF
12	Chang-Chih Chen, Linda Milor	System-level modeling and microprocessor reliability analysis for backend wearout mechanisms.	DATE	2013	DBLP DOI BibTeX RDF
12	Andrzej Kwiecien, Michal Mackowski, Marcin Sidzina	Data Security in Microprocessor Units.	CN	2013	DBLP DOI BibTeX RDF
12	Andrzej Kwiecien, Michal Mackowski, Krzysztof Skoroniak	The Concept of Software-Based Techniques of Increasing Immunity of Microprocessor Unit to Electromagnetic Disturbances.	CN	2013	DBLP DOI BibTeX RDF
12	Yap Hoon, Noor Ain Kamsani, Roslina Mohd Sidek, Nasri Sulaiman, Fakhrul Zaman Rokhani	Energy efficient 8-bit microprocessor for wireless sensor network applications.	ICEAC	2013	DBLP DOI BibTeX RDF
12	Gwo-Ching Chang	A microprocessor-based multichannel subsensory stochastic resonance electrical stimulator.	EMBC	2013	DBLP DOI BibTeX RDF
12	Ruchir Puri	Opportunities and challenges for high performance microprocessor designs and design automation.	ISPD	2013	DBLP DOI BibTeX RDF
12	Tim Barrass	Mozzi: Interactive sound synthesis on the Open Source Arduino Microprocessor.	ICMC	2013	DBLP BibTeX RDF
12	Michael Bauer, Daniel Lohn, Benjamin Betting, Uwe Brinkschulte	Design and evaluation of an adaptive real-time microprocessor.	ICES	2013	DBLP DOI BibTeX RDF
12	Ashraf Suyyagh, Benjamin Nahill, Alexandre Courtemanche, Evgeny Kirshin, Zeljko Zilic, Boris Karajica	Managing the microprocessor course scope expansion.	MSE	2013	DBLP DOI BibTeX RDF
12	Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco	Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms.	ICCAD	2013	DBLP DOI BibTeX RDF
12	Yier Jin, Yiorgos Makris	A proof-carrying based framework for trusted microprocessor IP.	ICCAD	2013	DBLP DOI BibTeX RDF
12	Xiaoping Huang, Jianfeng An	A Novel Architecture to Identify the Microprocessor Chips by Implanting Timing-Fault Execution Unit.	CSE	2013	DBLP DOI BibTeX RDF
12	Achim D. Brucker, Abderrahmane Feliachi, Yakoub Nemouchi, Burkhart Wolff	Test Program Generation for a Microprocessor - A Case-Study.	TAP@STAF	2013	DBLP DOI BibTeX RDF
12	Joaquin Gracia-Moran, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Juan-Carlos Baraza-Calvo, Pedro J. Gil-Vicente	Defining a Representative and Low Cost Fault Model Set for Intermittent Faults in Microprocessor Buses.	LADC	2013	DBLP DOI BibTeX RDF
12	James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb	5.5GHz system z microprocessor and multi-chip module.	ISSCC	2013	DBLP DOI BibTeX RDF
12	Alan J. Drake, Michael S. Floyd, Richard L. Willaman, Derek J. Hathaway, Joshua Hernandez, Crystal Soja, Marshall D. Tiner, Gary D. Carpenter, Robert M. Senger	Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor.	ISLPED	2013	DBLP DOI BibTeX RDF
12	Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Hui Huang 0001, Glenn Reinman	Composable accelerator-rich microprocessor enhanced for adaptivity and longevity.	ISLPED	2013	DBLP DOI BibTeX RDF
12	Sai Manoj Pudukotai Dinakarrao, Hao Yu 0001	Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor.	ISCAS	2013	DBLP DOI BibTeX RDF
12	Nikos Foutris, Dimitris Gizopoulos, John Kalamatianos, Vilas Sridharan	Measuring the performance impact of permanent faults in modern microprocessor architectures.	IOLTS	2013	DBLP DOI BibTeX RDF
12	Chang-Chih Chen, Linda Milor	System-level modeling and reliability analysis of microprocessor systems.	IWASI	2013	DBLP DOI BibTeX RDF
12	Joonho Kong, Sung Woo Chung	Process variation-tolerant 3D microprocessor design: An efficient architectural solution.	ICICDT	2013	DBLP DOI BibTeX RDF