Search results for "DSD"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Panayiotis Savvopoulos, Nikolaos Papandreou, Theodore Antonakopoulos 0001	Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator.	DSD	2009	DBLP DOI BibTeX RDF
1	Jimmy Tarrillo, Letícia Maria Veiras Bolzani Poehls, Fabian Vargas 0001	A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems.	DSD	2009	DBLP DOI BibTeX RDF
1	George Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu	Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology.	DSD	2009	DBLP DOI BibTeX RDF
1	Timo Schönwald, Jochen Zimmermann, Oliver Bringmann 0001, Wolfgang Rosenstiel	Network-on-Chip Architecture Exploration Framework.	DSD	2009	DBLP DOI BibTeX RDF
1	Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López 0001, José Duato	An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions.	DSD	2009	DBLP DOI BibTeX RDF
1	Jan Kastil, Jan Korenek, Ondrej Lengál	Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing.	DSD	2009	DBLP DOI BibTeX RDF
1	Simon Hollis	Pulse Generation for On-chip Data Transmission.	DSD	2009	DBLP DOI BibTeX RDF
1	Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid	A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC.	DSD	2009	DBLP DOI BibTeX RDF
1	Mario Alberto Ibarra-Manzano, Dora Luz Almanza-Ojeda, Michel Devy, Jean-Louis Boizard, Jean-Yves Fourniols	Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization.	DSD	2009	DBLP DOI BibTeX RDF
1	Joris Borms, Kris Steenhaut, Bart Lemmens, Ann Nowé	Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks.	DSD	2009	DBLP DOI BibTeX RDF
1	Maroun Ojail, Raphaël David, Stéphane Chevobbe, Didier Demigny	Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems.	DSD	2009	DBLP DOI BibTeX RDF
1	Rizwan Asghar, Di Wu 0003, Johan Eilert, Dake Liu	Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution.	DSD	2009	DBLP DOI BibTeX RDF
1	Marcel Steine, Marco Bekooij, Maarten Wiggers	A Priority-Based Budget Scheduler with Conservative Dataflow Model.	DSD	2009	DBLP DOI BibTeX RDF
1	Alexandre Guerre, Nicolas Ventroux, Raphaël David, Alain Mérigot	Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study.	DSD	2009	DBLP DOI BibTeX RDF
1	Marius Gligor, Nicolas Fournel, Frédéric Pétrot	Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture.	DSD	2009	DBLP DOI BibTeX RDF
1	Asadollah Shahbahrami, Ben H. H. Juurlink	SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform.	DSD	2009	DBLP DOI BibTeX RDF
1	Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura	Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables.	DSD	2009	DBLP DOI BibTeX RDF
1	James Mathews, Matthew Barnes, D. K. Arvind 0001	Low Power Free Space Optical Communication in Wireless Sensor Networks.	DSD	2009	DBLP DOI BibTeX RDF
1	Demid Borodin, Ben H. H. Juurlink, Stefanos Kaxiras	Instruction Precomputation for Fault Detection.	DSD	2009	DBLP DOI BibTeX RDF
1	Roland Dobai, Elena Gramatová	Deductive Fault Simulation for Asynchronous Sequential Circuits.	DSD	2009	DBLP DOI BibTeX RDF
1	Amir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani, Mahmood Fathy, Reza Berangi	A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction.	DSD	2009	DBLP DOI BibTeX RDF
1	Perfecto Mariño Espiñeira, Fernando Pérez-Fontán, Miguel Angel Domínguez, Santiago Otero	Ad-hoc WSN in Biological Research.	DSD	2009	DBLP DOI BibTeX RDF
1	Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip.	DSD	2009	DBLP DOI BibTeX RDF
1	Richard Ruzicka	Dependable Controller Design Using Polymorphic Counters.	DSD	2009	DBLP DOI BibTeX RDF
1	Sven Rosinger, Kiril Schröder, Wolfgang Nebel	Power Management Aware Low Leakage Behavioural Synthesis.	DSD	2009	DBLP DOI BibTeX RDF
1	Minwook Ahn, Jonghee M. Youn, Youngkyu Choi, Doosan Cho, Yunheung Paek	Iterative Algorithm for Compound Instruction Selection with Register Coalescing.	DSD	2009	DBLP DOI BibTeX RDF
1	Lu Gao, Li Guo, Canxing Lu	Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers.	DSD	2009	DBLP DOI BibTeX RDF
1	Václav Simek, Radim Dvorak, Frantisek Zboril, Vladimír Drábek	GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations.	DSD	2009	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen	An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs.	DSD	2009	DBLP DOI BibTeX RDF
1	Ozgur Tasdizen, Ilker Hamzaoglu	A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video.	DSD	2009	DBLP DOI BibTeX RDF
1	Makoto Sugihara	Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints.	DSD	2009	DBLP DOI BibTeX RDF
1	Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias	Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs.	DSD	2009	DBLP DOI BibTeX RDF
1	George Economakos, Sotirios Xydis	Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis.	DSD	2009	DBLP DOI BibTeX RDF
1	George Economakos, Sotirios Xydis	A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
1	Shahid Mehmood, Stefano Cagnoni, Monica Mordonini, Guido Matrella	Hardware-oriented Adaptation of a Particle Swarm Optimization Algorithm for Object Detection.	DSD	2008	DBLP DOI BibTeX RDF
1	Sudip Roy 0001, Ajit Pal	Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?	DSD	2008	DBLP DOI BibTeX RDF
1	A. Neslin Ismailoglu, Murat Askar	SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.	DSD	2008	DBLP DOI BibTeX RDF
1	Sharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi	Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations.	DSD	2008	DBLP DOI BibTeX RDF
1	Radek Dobias, Jan Konarski, Hana Kubátová	Dependability Evaluation of Real Railway Interlocking Device.	DSD	2008	DBLP DOI BibTeX RDF
1	Francesco Sechi, Luca Fanucci, Stefano Luschi, Simone Perini, Matteo Madesani	Design of a Distributed Embedded System for Domotic Applications.	DSD	2008	DBLP DOI BibTeX RDF
1	Alberto Ferrante, Simone Medardoni, Davide Bertozzi	Network Interface Sharing Techniques for Area Optimized NoC Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Lech Józwiak, Szymon Bieganski	Technology Library Modelling for Information-driven Circuit Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
1	Pedro Garcia-Repetto, María C. Molina, Rafael Ruiz-Sautua, Guillermo Botella Juan	Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits.	DSD	2008	DBLP DOI BibTeX RDF
1	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström	Leveraging Data Promotion for Low Power D-NUCA Caches.	DSD	2008	DBLP DOI BibTeX RDF
1	Carlo Brandolese	Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software.	DSD	2008	DBLP DOI BibTeX RDF
1	Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata	SIMD Enhancements for a Hough Transform Implementation.	DSD	2008	DBLP DOI BibTeX RDF
1	Toshimasa Funaki, Toshinori Sato	Formulating MITF for a Multicore Processor with SEU Tolerance.	DSD	2008	DBLP DOI BibTeX RDF
1	Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng	Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems.	DSD	2008	DBLP DOI BibTeX RDF
1	Goran Panic, Daniel Dietterle, Zoran Stamenkovic	Architecture of a Power-Gated Wireless Sensor Node.	DSD	2008	DBLP DOI BibTeX RDF
1	Alessandro Cilardo, Nicola Mazzocca, Luigi Coppolino	Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems.	DSD	2008	DBLP DOI BibTeX RDF
1	Jiri Jenícek	Efficient Test Pattern Compression Method Using Hard Fault Preferring.	DSD	2008	DBLP DOI BibTeX RDF
1	Sebastien Fontaine, Luc Filion, Guy Bois	Exploring ISS Abstractions for Embedded Software Design.	DSD	2008	DBLP DOI BibTeX RDF
1	Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot	Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform.	DSD	2008	DBLP DOI BibTeX RDF
1	Theja Tulabandhula, Amit Patra, Nirmal B. Chakrabarti	Design of a Two Dimensional PRSI Image Processor.	DSD	2008	DBLP DOI BibTeX RDF
1	Zhen Liu 0018, Jia Yu 0008, Xiaojun Wang 0001, Bin Liu 0001, Laxmi N. Bhuyan	Revisiting the Cache Effect on Multicore Multithreaded Network Processors.	DSD	2008	DBLP DOI BibTeX RDF
1	Carlo Brandolese, William Fornaciari	Measurement, Analysis and Modeling of RTOS System Calls Timing.	DSD	2008	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Antonio Miele, Donatella Sciuto	Fault Models and Injection Strategies in SystemC Specifications.	DSD	2008	DBLP DOI BibTeX RDF
1	Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Sven-Arne Reinemo	An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures.	DSD	2008	DBLP DOI BibTeX RDF
1	Simone Campanoni, William Fornaciari	Models and Tradeoffs in WSN System-Level Design.	DSD	2008	DBLP DOI BibTeX RDF
1	Giacomo Paci, Axel Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal	How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design.	DSD	2008	DBLP DOI BibTeX RDF
1	Pedro Miguens Matutino, Leonel Sousa	An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences.	DSD	2008	DBLP DOI BibTeX RDF
1	Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink	Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture.	DSD	2008	DBLP DOI BibTeX RDF
1	Ming Liu 0011, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch	System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments.	DSD	2008	DBLP DOI BibTeX RDF
1	Huiju Cheng, Howard M. Heys, Cheng Wang	PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems.	DSD	2008	DBLP DOI BibTeX RDF
1	Tsau-Shuan Wu, Alkan Cengiz, Tom W. Chen	Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking.	DSD	2008	DBLP DOI BibTeX RDF
1	Yoonjin Kim, Rabi N. Mahapatra	A New Array Fabric for Coarse-Grained Reconfigurable Architecture.	DSD	2008	DBLP DOI BibTeX RDF
1	Martin Straka, Zdenek Kotásek, Jan Winter	Digital Systems Architectures Based on On-line Checkers.	DSD	2008	DBLP DOI BibTeX RDF
1	Petr Mikusek, Vaclav Dvorak	On Lookup Table Cascade-Based Realizations of Arbiters.	DSD	2008	DBLP DOI BibTeX RDF
1	Shruti Patil, Venkatesan Muthukumar	Maximizing Resource Utilization by Slicing of Superscalar Architecture.	DSD	2008	DBLP DOI BibTeX RDF
1	Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato	CART: Communication-Aware Routing Technique for Application-Specific NoCs.	DSD	2008	DBLP DOI BibTeX RDF
1	Andrzej Krasniewski	Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs.	DSD	2008	DBLP DOI BibTeX RDF
1	Nuno Sebastião, Tiago Dias 0001, Nuno Roma, Paulo F. Flores, Leonel Sousa	Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units.	DSD	2008	DBLP DOI BibTeX RDF
1	Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton	A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Laurent Alaus, Dominique Noguet, Jacques Palicot	A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis.	DSD	2008	DBLP DOI BibTeX RDF
1	Jirí Kvasnicka, Pavel Kubalík, Hana Kubátová	Experimental SEU Impact on Digital Design Implemented in FPGAs.	DSD	2008	DBLP DOI BibTeX RDF
1	Primoz Puhar, Andrej Zemva	Functional Verification of a USB Host Controller.	DSD	2008	DBLP DOI BibTeX RDF
1	Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.	DSD	2008	DBLP DOI BibTeX RDF
1	Enrique San Millán, Luis Entrena, José Alberto Espejo	Logic Transformations by Multiple Wire Network Addition.	DSD	2008	DBLP DOI BibTeX RDF
1	Sergio Saponara, Francesco Vitullo, Riccardo Locatelli, Philippe Teninge, Marcello Coppola, Luca Fanucci	LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control.	DSD	2008	DBLP DOI BibTeX RDF
1	Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi	Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm.	DSD	2008	DBLP DOI BibTeX RDF
1	Paola Baldrighi, Marco Maurizio Maggi, Marco Castellano, Carla Vacchi, Davide Crespi, Piero Bonifacino	Implementation of Microprogrammed Hard Disk Drive Servo Sequencer.	DSD	2008	DBLP DOI BibTeX RDF
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Development of Functional Delay Tests.	DSD	2008	DBLP DOI BibTeX RDF
1	Ruimin Huang, Niklas Lotze, Yiannos Manoli	On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip.	DSD	2008	DBLP DOI BibTeX RDF
1	Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez	Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration.	DSD	2008	DBLP DOI BibTeX RDF
1	Morteza Damavandpeyma, Siamak Mohammadi	Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool.	DSD	2008	DBLP DOI BibTeX RDF
1	Paris Kitsos, George N. Selimis, Odysseas G. Koufopavlou, Athanassios N. Skodras	A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors.	DSD	2008	DBLP DOI BibTeX RDF
1	Christophe Le Blanc, Éric Colinet, Jérôme Juillard, Lorena Anghel	Digital Implementation of a BIST Method based on Binary Observations.	DSD	2008	DBLP DOI BibTeX RDF
1	Blaz Lampreht, Luka Stepancic, Igor Vizec, Bostjan Zankar, Miha Mraz, Iztok Lebar Bajec, Primoz Pecar	Quantum-Dot Cellular Automata Serial Comparator.	DSD	2008	DBLP DOI BibTeX RDF
1	R. Morales-Ramos, Alexander Vaz, Daniel Pardo 0001, Roc Berenguer	Ultra-Low Power Passive UHF RFID for Wireless Sensor Networks.	DSD	2008	DBLP DOI BibTeX RDF
1	Roberto Giorgi, Paolo Bennati	Reducing Leakage through Filter Cache.	DSD	2008	DBLP DOI BibTeX RDF
1	Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram	Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing.	DSD	2008	DBLP DOI BibTeX RDF
1	Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania	Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links.	DSD	2008	DBLP DOI BibTeX RDF
1	Muhammad Rashid, Damien Picard, Bernard Pottier	Application Analysis for Parallel Processing.	DSD	2008	DBLP DOI BibTeX RDF
1	Tsutomu Sasao, Yukihiro Iguchi	On the Complexity of Error Detection Functions for Redundant Residue Number Systems.	DSD	2008	DBLP DOI BibTeX RDF
1	Ismael Gómez, Vuk Marojevic, José Salazar, Antoni Gelonch	A Lightweight Operating Environment for Next Generation Cognitive Radios.	DSD	2008	DBLP DOI BibTeX RDF
1	Gottfried Fuchs, Matthias Függer, Ulrich Schmid 0001, Andreas Steininger	Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip.	DSD	2008	DBLP DOI BibTeX RDF
1	Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida	Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
1	Ahmed Abdallah, Wayne H. Wolf, Graham R. Hellestrand	Using Empirical Science to Engineer Systems: Optimizing Cache for Power and Performance.	DSD	2008	DBLP DOI BibTeX RDF
1	Luca Fanucci (eds.)	11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008	DSD	2008	DBLP BibTeX RDF
1	Alessandro Mignogna, Massimo Conti, M. D'Angelo, Massimo Baleani, Alberto Ferrari	Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard.	DSD	2008	DBLP DOI BibTeX RDF

Publications at "DSD"( http://dblp.L3S.de/Venues/DSD )