Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Yuji Sato	Proposal for a field-evolvable hardware based on a microprocessor incorporated flash memory.	CEC	2001	DBLP DOI BibTeX RDF
12	Nabarun Bhattacharyya, A. Wang	Automatic test generation for micro-architectural verification of configurable microprocessor cores with user extensions.	HLDVT	2001	DBLP DOI BibTeX RDF
12	Shuvendu K. Lahiri, Carl Pixley, Ken Albin	Experience with term level modeling and verification of the M*CORE TM microprocessor core.	HLDVT	2001	DBLP DOI BibTeX RDF
12	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	FPGA-Based Fault Injection for Microprocessor Systems.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
12	Y. Lin, L. E. Turner, Martin P. Mintchev	Design of a portable microprocessor-based stimulator for the recreation of impaired gastrointestinal motility.	ICECS	2001	DBLP DOI BibTeX RDF
12	Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones	A Framework for Microprocessor Correctness Statements.	CHARME	2001	DBLP DOI BibTeX RDF
12	Chia-Hung Kuo, Behnam S. Arad	Design and Simulation of a Pipelined Microprocessor.	CAINE	2001	DBLP BibTeX RDF
12	Tamotsu Miyake, Takeo Yamashita, Norikatsu Asari, Hideki Sekisaka, Tom Sakai, Kazuhiro Matsuura, Atsushi Wakahara, Hideyuki Takahashi, Tom Hiyama, Kazuhisa Miyamoto, Kazutaka Mori	Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS.	CICC	2001	DBLP DOI BibTeX RDF
12	Howard H. Smith, Aline Deutsch, Sharad Mehrotra, David Widiger, Michael A. Bowen, Allan H. Dansky, Gerard V. Kopcsay, Byron Krauter	R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip.	CICC	2001	DBLP DOI BibTeX RDF
12	Frank Vahid, Ann Gordon-Ross	A self-optimizing embedded microprocessor using a loop table for low power.	ISLPED	2001	DBLP DOI BibTeX RDF	parameterized architectures, self-optimizing architecture, embedded systems, low-power, system-on-a-chip, platforms, cores, tuning
12	John Paul Shen	Clear and Present Tensions in Microprocessor Design.	ICCD	2001	DBLP DOI BibTeX RDF
12	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static Energy Reduction Techniques for Microprocessor Caches.	ICCD	2001	DBLP DOI BibTeX RDF
12	Seongwoo Kim, Arun K. Somani	On-Line Integrity Monitoring of Microprocessor Control Logic.	ICCD	2001	DBLP DOI BibTeX RDF
12	Mauro Olivieri, Alessandro Trifiletti	An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Sergio L. Toral Marín, José M. Quero, Mar M. Elena Pérez, Leopoldo García Franquelo	A microprocessor based system for ECG telemedicine and telecare.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Mauro Olivieri	A genetic approach to the design space exploration of superscalar microprocessor architectures.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
12	Ram Krishnamurthy 0001, Mark A. Anders 0001, Krishnamurthy Soumyanath, Shekhar Borkar	Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
12	Gilbert Vandling	Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo.	ITC	2001	DBLP DOI BibTeX RDF
12	Mary P. Kusko, Bryan J. Robbins, Timothy J. Koprowski, William V. Huott	99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor.	ITC	2001	DBLP DOI BibTeX RDF
12	Sei Takahashi, Munehisa Taira, Hidetaka Saegusa, Takehiko Hoshino, Hideo Nakamura	Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature.	PRDC	2001	DBLP DOI BibTeX RDF
12	Rajagopalan Desikan, Doug Burger, Stephen W. Keckler	Measuring Experimental Error in Microprocessor Simulation.	ISCA	2001	DBLP DOI BibTeX RDF
12	Bob Bentley	Validating the Intel Pentium 4 Microprocessor.	DAC	2001	DBLP DOI BibTeX RDF
12	Richard Lee, Benjamin Tsien	Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System.	DAC	2001	DBLP DOI BibTeX RDF
12	Gregory A. Northrop, Pong-Fei Lu	A Semi-Custom Design Flow in High-Performance Microprocessor Design.	DAC	2001	DBLP DOI BibTeX RDF
12	Robert Müller 0002	Fingerprint verification with microprocessor security tokens.		2001	RDF
12	Ali El-Hajj, Karim Y. Kabalan, Maher N. Mneimneh, Feras Karablieh	Microprocessor Simulation and Program Assembling Using Spreadsheets.	Simul.	2000	DBLP DOI BibTeX RDF
12	Hee-Tae Ahn, David J. Allstot	A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
12	Simon Tam 0001, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, Ian Young 0001	Clock generation and distribution for the first IA-64 microprocessor.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
12	Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani	A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
12	Stefan Rusu, Gadi Singer	The first IA-64 microprocessor.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
12	Thomas D. Burd, Trevor Pering, Anthony J. Stratakos, Robert W. Brodersen	A dynamic voltage scaled microprocessor system.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
12	Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You	A third-generation SPARC V9 64-b microprocessor.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
12	William C. Athas, Nestoras Tzartzanis, Weihua Mao, Lena Peterson, Rajat Lal, Kisup Chong, Joong-Seok Moon, Lars J. Svensson, Michael Bolotski	The design and implementation of a low-power clock-powered microprocessor.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
12	David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel	Custom circuit design as a driver of microprocessor performance.	IBM J. Res. Dev.	2000	DBLP DOI BibTeX RDF
12	Charles F. Webb	S/390 microprocessor design.	IBM J. Res. Dev.	2000	DBLP DOI BibTeX RDF
12	Todd M. Austin	DIVA: A Dynamic Approach to Microprocessor Verification.	J. Instr. Level Parallelism	2000	DBLP BibTeX RDF
12	John N. Coleman, E. I. Chester, Christopher I. Softley, Jiri Kadlec	Corrections to 'Arithmetic on the European Logarithmic Microprocessor'.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF
12	Pantelis N. Botsaris, A. Polyhroniadis	Microprocessor controlled exhaust gas lambda sensor.	Microprocess. Microsystems	2000	DBLP DOI BibTeX RDF
12	Eduardo Augusto Bezerra, Michael Paul Gough	A guide to migrating from microprocessor to FPGA coping with the support tool limitations.	Microprocess. Microsystems	2000	DBLP DOI BibTeX RDF
12	M. Watheq El-Kharashi, F. Elguibaly, Kin F. Li	A quantitative study for Java microprocessor architectural requirements. Part I: Instruction set design.	Microprocess. Microsystems	2000	DBLP DOI BibTeX RDF
12	M. Watheq El-Kharashi, F. Elguibaly, Kin F. Li	A quantitative study for Java microprocessor architectural requirements. Part II: high-level language support.	Microprocess. Microsystems	2000	DBLP DOI BibTeX RDF
12	Takashi Ebihara, Yasushi Ishikawa, Yasuhisa Kisuki, Tadashi Sakamoto, Tomohiro Hase	Speech synthesis software with a variable speaking rate and its implementation on a 32-bit microprocessor.	IEEE Trans. Consumer Electron.	2000	DBLP DOI BibTeX RDF
12	Go Sato, Takashi Asai, Tadashi Sakamoto, Tomohiro Hase	Improvement of the positioning accuracy of a software-based GPS receiver using a 32-bit embedded microprocessor.	IEEE Trans. Consumer Electron.	2000	DBLP DOI BibTeX RDF
12	Jae Wook Jeon	A microprocessor course: designing and implementing personal microcomputers.	IEEE Trans. Educ.	2000	DBLP DOI BibTeX RDF
12	Richard B. Brown, Ronald J. Lomax, Gordon A. Carichner, Alan J. Drake	A microprocessor design project in an introductory VLSI course.	IEEE Trans. Educ.	2000	DBLP DOI BibTeX RDF
12	Keith A. Jenkins, James P. Eckhardt	Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
12	Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng	Functionally Testable Path Delay Faults on a Microprocessor.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
12	Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham	Validating PowerPC Microprocessor Custom Memories.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
12	Alfred L. Crouch, Michael Mateja, Teresa L. McLaurin, John C. Potter, Dat Tran	Test Development for a Third-Version ColdFire Microprocessor.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
12	Magdy S. Abadir, Sumit Dasgupta	Guest Editors' Introduction: Microprocessor Test and Verification.	IEEE Des. Test Comput.	2000	DBLP BibTeX RDF
12	Andrew Burdass, Gary Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York	Microprocessor cores.	ETW	2000	DBLP DOI BibTeX RDF
12	Jun Kikuchi, Tetsuo Sasaki, Tohru Hashimoto, Kazuhisa Miyamoto	Delay-optimal wiring plan for the microprocessor of high performance computing machines.	ASP-DAC	2000	DBLP DOI BibTeX RDF
12	Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka	Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system.	ASP-DAC	2000	DBLP DOI BibTeX RDF
12	Fujio Ishihara, Christian Klinger, Ken-ichi Agawa	Clock design of 300MHz 128-bit 2-way superscalar microprocessor.	ASP-DAC	2000	DBLP DOI BibTeX RDF
12	Norman Kojima, Yukiko Parameswar, Christian Klingner, Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda, Kouji Hashizume, Haruyuki Tago, Masaaki Yamada	Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor.	ASP-DAC	2000	DBLP DOI BibTeX RDF
12	David M. Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose	Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.	PACS	2000	DBLP DOI BibTeX RDF
12	Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube	Formal Verification of a Reconfigurable Microprocessor.	FPL	2000	DBLP DOI BibTeX RDF
12	Jess Rupley II, David C. Holloway	Performance tradeoffs in sequencer design on a new G4 PowerPCTM microprocessor.	ISPASS	2000	DBLP DOI BibTeX RDF
12	Tsvetozar Georgiev, Angel Smrikarov, Dimitar Stanchev	Advanced microprocessor system for testing the dynamic properties of road vehicles.	CompSysTech	2000	DBLP DOI BibTeX RDF
12	Wadih Zaatar, George E. Nasr	An implementation scheme for a microprocessor emulator.	ICECS	2000	DBLP DOI BibTeX RDF
12	Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy	Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor.	ISPD	2000	DBLP DOI BibTeX RDF	RC delay, routing, timing, estimation, microprocessors, floorplan, repeaters
12	Lode Nachtergaele, Vivek Tiwari, Nikil D. Dutt	System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications.	ICCAD	2000	DBLP DOI BibTeX RDF
12	Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor.	CICC	2000	DBLP DOI BibTeX RDF
12	Trevor Pering, Thomas D. Burd, Robert W. Brodersen	Voltage scheduling in the IpARM microprocessor system.	ISLPED	2000	DBLP DOI BibTeX RDF	low-power, energy-efficient, operating systems, RTOS
12	Yi-Kan Cheng, David Bearden, Kanti Suryadevara	Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPCTM Microprocessor.	ICCD	2000	DBLP DOI BibTeX RDF
12	Piotr Dudek, Peter J. Hicks	A CMOS general-purpose sampled-data analogue microprocessor.	ISCAS	2000	DBLP DOI BibTeX RDF
12	Christian Jacobi 0002, Daniel Kroening	Proving the Correctness of a Complete Microprocessor.	GI Jahrestagung	2000	DBLP DOI BibTeX RDF
12	Jayanta Batra, Magdy S. Abadir, Jacob A. Abraham	A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor.	LATW	2000	DBLP BibTeX RDF
12	Teresa L. McLaurin, Frank Frederick	The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core.	ITC	2000	DBLP DOI BibTeX RDF
12	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	Test program synthesis for path delay faults in microprocessor cores.	ITC	2000	DBLP DOI BibTeX RDF
12	Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan	DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor.	ITC	2000	DBLP DOI BibTeX RDF
12	Teresa L. McLaurin, John C. Potter	On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores.	ITC	2000	DBLP DOI BibTeX RDF
12	Farideh Golshan	Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor.	ITC	2000	DBLP DOI BibTeX RDF
12	Anjali Kinra, Hari Balachandran, Regy Thomas, John Carulli	Logic mapping on a microprocessor.	ITC	2000	DBLP DOI BibTeX RDF
12	Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe	Jitter measurements of a PowerPCTM microprocessor using an analytic signal method.	ITC	2000	DBLP DOI BibTeX RDF
12	Kevin Skadron	A microprocessor survey course: exploring advanced computer architecture in practice.	WCAE	2000	DBLP DOI BibTeX RDF
12	Steven K. Reinhardt	Integrating hardware and software concepts in a microprocessor-based system design lab.	WCAE	2000	DBLP DOI BibTeX RDF
12	Mark Oskin, Frederic T. Chong, Matthew K. Farrens	HLS: combining statistical and symbolic simulation to guide microprocessor designs.	ISCA	2000	DBLP DOI BibTeX RDF
12	Vikram Iyengar, Elizabeth M. Rudnick	Microprocessor Design Verification.	The VLSI Handbook	1999	DBLP DOI BibTeX RDF
12	Tanay Karnik	Microprocessor Layout Method.	The VLSI Handbook	1999	DBLP DOI BibTeX RDF
12	Tzuen-Lih Chern, Jerome Chang, Chien-Hung Chen, Hann-Tzong Su	Microprocessor-based modified discrete integral variable-structure control for UPS.	IEEE Trans. Ind. Electron.	1999	DBLP DOI BibTeX RDF
12	Michael Golden, Steve Hesley, Alisa Scherer, Matthew Crowley, Scott C. Johnson, Stephan Meier, Dirk Meyer, Jerry D. Moench, Stuart F. Oberman, Hamid Partovi, Fred Weber, Scott White, Tim Wood 0001, John Yong	A seventh-generation x86 microprocessor.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
12	Ramesh Senthinathan, Stephen Fischer, Hamid Rangchi, Hadi Yazdanmehr	A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
12	Masakazu Suzuoki, Ken Kutaragi, Toshiyuki Hiroi, Hidetaka Magoshi, Shin'ichi Okamoto, Masaaki Oka, Akio Ohba, Yasuyuki Yamamoto, Makoto Furuhashi, Masayoshi Tanaka, Teiji Yutaka, Toyoshi Okada, Masato Nagamatsu, Yukihiro Urakawa, Masami Funyu, Atsushi Kunimatsu, Harutaka Goto, Kazuhiro Hashimoto, Nobuhiro Ide, Hiroaki Murakami, Yukio Ohtaguro, Akira Aono	A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
12	Carmine Nicoletta, Jose Alvarez, Eric Barkin, Chai-Chin Chao, Brad R. Johnson, Franklin M. Lassandro, Paresh Patel, Douglas Reid, Hector Sanchez, Joshua Siegel, Michael Snyder, Steven Sullivan, Scott A. Taylor, Minh Vo	A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
12	Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama	An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
12	Sung Bae Park, Young Wug Kim, Young Gun Ko, Kwang Il Kim, Il Kwon Kim, Hee-Sung Kang, Jin Oh Yu, Kwang Pyuk Suh	A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
12	Anthony G. Aipperspach, David H. Allen, Dennis T. Cox, Nghia Phan, Salvatore N. Storino	A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
12	Michael J. Flynn, Patrick Hung, Kevin W. Rudd	Deep submicron microprocessor design issues.	IEEE Micro	1999	DBLP DOI BibTeX RDF
12	Timothy J. Slegel, Robert M. Averill III, Mark A. Check, Bruce C. Giamei, Barry Krumm, Christopher A. Krygowski, W. H. Li, John S. Liptay, John D. MacDougall, Thomas J. McPherson, Jennifer A. Navarro, Eric M. Schwarz, Chung-Lung Kevin Shum, Charles F. Webb	IBM's S/390 G5 microprocessor design.	IEEE Micro	1999	DBLP DOI BibTeX RDF
12	Richard E. Kessler	The Alpha 21264 microprocessor.	IEEE Micro	1999	DBLP DOI BibTeX RDF
12	Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda	Fault Injection for Embedded Microprocessor-based Systems.	J. Univers. Comput. Sci.	1999	DBLP DOI BibTeX RDF
12	Peilin Song, Franco Motika, Daniel R. Knebel, Richard F. Rizzolo, Mary P. Kusko	S/390 G5 CMOS microprocessor diagnostics.	IBM J. Res. Dev.	1999	DBLP DOI BibTeX RDF
12	Matt Reilly	Designing an Alpha Microprocessor.	Computer	1999	DBLP DOI BibTeX RDF
12	Douglas J. Leith, William E. Leithead	On microprocessor-based arc voltage control for gas tungsten arc welding using gain scheduling.	IEEE Trans. Control. Syst. Technol.	1999	DBLP DOI BibTeX RDF
12	Yasushi Ishikawa, Yasuhisa Kisuki, Tadashi Sakamoto, Tomohiro Hase	Speech synthesis method based on application-specific synthesis units and its implementation on a 32-bit microprocessor.	IEEE Trans. Consumer Electron.	1999	DBLP DOI BibTeX RDF
12	Yong Zhang, Kai-Kuang Ma, Qingdong Yao	A software/hardware co-design methodology for embedded microprocessor core design.	IEEE Trans. Consumer Electron.	1999	DBLP DOI BibTeX RDF
12	Michael J. Flynn	Basic issues in microprocessor architecture.	J. Syst. Archit.	1999	DBLP DOI BibTeX RDF
12	David H. Albonesi, Israel Koren	STATS: A framework for microprocessor and system-level design space exploration.	J. Syst. Archit.	1999	DBLP DOI BibTeX RDF
12	Alessandro De Gloria	Microprocessor design for embedded system.	J. Syst. Archit.	1999	DBLP DOI BibTeX RDF