Search results for "ADC-BiST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Yongsheng Wang, Jinxiang Wang 0001, Fengchang Lai, Yizheng Ye	Optimal Schemes for ADC BIST Based on Histogram.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
65	Brendan Mullane, Ciaran MacNamee, Vincent O'Brien, Thomas Fleischmann	An on-chip solution for static ADC test and measurement.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ADC-BiST, code histogram, linearity measurements, test, system-on-chip, analog to digital converter
56	Hung-Kai Chen 0001, Chih-Hu Wang, Chau-Chin Su	A Self Calibrated ADC BIST Methodology.	VTS	2002	DBLP DOI BibTeX RDF
38	Xiankun Jin, Tao Chen 0006, Mayank Jain, Arun Kumar Barman, David Kramer, Doug Garrity, Randall L. Geiger, Degang Chen 0001	An on-chip ADC BIST solution and the BIST enabled calibration scheme.	ITC	2017	DBLP DOI BibTeX RDF
34	Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong	Multi-histogram ADC BIST System for ADC Linearity Testing.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
30	Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento	Low Cost BIST for Static and Dynamic Testing of ADCs.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	ADC BIST, noise based testing, mixed-signal test
26	Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell	A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	Built-In Self-Test (BIST), analog and mixed-signal testing, ADC test
24	Senthil Sivakumar, S. P. Joy Vasantha Rani	Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
24	Senthil Sivakumar, S. P. Joy Vasantha Rani	An ADC BIST using on-chip ramp generation and digital ORA.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
24	Hao Meng, Degang Chen 0001	A simple ramp generator with level spreading for SEIR based ADC BIST circuit.	MWSCAS	2015	DBLP DOI BibTeX RDF
24	Yan Duan, Tao Chen 0006, Zhiqiang Liu, Xu Zhang, Degang Chen 0001	High-constancy offset generator robust to CDAC nonlinearity for SEIR-based ADC BIST.	ISCAS	2015	DBLP DOI BibTeX RDF
24	Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán	Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
24	Jingbo Duan, Bharath K. Vasan, Chen Zhao, Degang Chen 0001, Randall L. Geiger	On Chip Signal Generators for Low Overhead ADC BIST.	J. Electron. Test.	2012	DBLP DOI BibTeX RDF
24	Jingbo Duan, Degang Chen 0001, Randall L. Geiger	A low cost method for testing offset and gain error for ADC BIST.	ISCAS	2012	DBLP DOI BibTeX RDF
24	Jingbo Duan, Degang Chen 0001	SNR measurement based on linearity test for ADC BIST.	ISCAS	2011	DBLP DOI BibTeX RDF
24	An-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting	A SAR ADC BIST for simplified linearity test.	SoCC	2011	DBLP DOI BibTeX RDF
24	Jingbo Duan, Le Jin, Degang Chen 0001	INL based dynamic performance estimation for ADC BIST.	ISCAS	2010	DBLP DOI BibTeX RDF
24	Jingbo Duan, Degang Chen 0001, Randall L. Geiger	Phase control of triangular stimulus generator for ADC BIST.	ISCAS	2010	DBLP DOI BibTeX RDF
24	Jingbo Duan, Degang Chen 0001, Randall L. Geiger	Cost Effective Signal Generators for ADC BIST.	ISCAS	2009	DBLP DOI BibTeX RDF
24	Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang	Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reconfigurable oscillator, Sinusoidal signal generator, Sigma-delta modulator
24	Erdem Serkan Erdogan, Sule Ozev	An ADC-BiST scheme using sequential code analysis.	DATE	2007	DBLP DOI BibTeX RDF
24	Dongmyung Lee, Kwisung Yoo, Kicheol Kim, Gunhee Han, Sungho Kang	Code-width testing-based compact ADC BIST circuit.	IEEE Trans. Circuits Syst. II Express Briefs	2004	DBLP DOI BibTeX RDF
24	Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell	On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF
24	Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell	Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	Built-In Self-Test (BIST), analog and mixed-signal testing, ADC test
24	Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell	On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.	VLSI-SOC	2001	DBLP BibTeX RDF
24	Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell	Towards an ADC BIST scheme using the histogram test technique.	ETW	2000	DBLP DOI BibTeX RDF
24	Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand	Hardware Resource Minimization for Histogram-Based ADC BIST.	VTS	2000	DBLP DOI BibTeX RDF
24	Stephen K. Sunter, Naveena Nagi	A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST.	ITC	1997	DBLP DOI BibTeX RDF