Search results for "ATPGs"

Found 17 publication records. Showing 17 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
64	Franco Fummi, Graziano Pravadelli	Logic-level analysis of high-level faults.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	fault models, functional verification
57	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
40	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, R. Mosca	Advanced Techniques for GA-based sequential ATPGs.	ED&TC	1996	DBLP DOI BibTeX RDF
40	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs.	ITC	1996	DBLP DOI BibTeX RDF
40	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach.	ITC	1996	DBLP DOI BibTeX RDF
21	Davide Bresolin, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Tiziano Villa	The impact of EFSM composition on functional ATPG.	DDECS	2009	DBLP DOI BibTeX RDF
21	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	EFSM Manipulation to Increase High-Level ATPG Effectiveness.	ISQED	2006	DBLP DOI BibTeX RDF
21	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	Improving Gate-Level ATPG by Traversing Concurrent EFSMs.	VTS	2006	DBLP DOI BibTeX RDF
21	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Low power test generation for path delay faults using stability functions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults
21	Santanu Chattopadhyay, Naveen Choudhary	Genetic Algorithm based Approach for Low Power Combinational Circuit Testing.	VLSI Design	2003	DBLP DOI BibTeX RDF
21	Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto	Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Testing of embedded systems, VHDL, ATPG, fault modeling, testability analysis
21	Maria K. Michael, Spyros Tragoudas	ATPG for Path Delay Faults without Path Enumeration.	ISQED	2001	DBLP DOI BibTeX RDF
21	Janusz Sosnowski, Tomasz Wabia, Tomasz Bech	Path Delay Fault Testability Analysis.	DFT	2000	DBLP DOI BibTeX RDF
21	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	High-Level Observability for Effective High-Level ATPG.	VTS	2000	DBLP DOI BibTeX RDF
21	Silvia Chiusano, Fulvio Corno, Paolo Prinetto	RT-level TPG Exploiting High-Level Synthesis Information.	VTS	1999	DBLP DOI BibTeX RDF
21	Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi	On a Logical Fault Model H1SGLF for Enhancing Defect Coverage.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
21	Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto	Implicit test generation for behavioral VHDL models.	ITC	1998	DBLP DOI BibTeX RDF