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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 42 occurrences of 34 keywords
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Results
Found 29 publication records. Showing 28 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
104 | Zair Abdelouahab, Peter M. Dew |
Programming concurrency and synchronisation in Actel. |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
Actel, concurrent object based language, performance, concurrency, object orientation, message passing, synchronisation, object-oriented languages, parallel languages |
84 | Jae-Tack Yoo, Erik Brunvand, Kent F. Smith |
Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC |
78 | Shashidhar Thakur, D. F. Wong 0001 |
On Designing ULM-based FPGA Logic Modules. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
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58 | Ingo Schäfer, Marek A. Perkowski |
Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
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54 | Milos Drutarovský, Michal Varchola |
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
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54 | Santanu Chattopadhyay, Manas Kumar Dewangan |
A Combinational Logic Mapper for Actel's SX/AX Family. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
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51 | Shomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu |
Customized Algorithms for High Performance Memory Test in Advanced Technology Node. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
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50 | A. Pal, R. K. Gorai, V. V. S. S. Raju |
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach |
39 | Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi |
Testing and testable designs for one-time programmable FPGAs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
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39 | Chih-Chang Lin, Malgorzata Marek-Sadowska |
On designing universal logic blocks and their application to FPGA design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
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34 | Olga Melnikova |
Overview of the prototyping technologies for Actel® RTAX-S FPGAs. |
EWDTS |
2011 |
DBLP DOI BibTeX RDF |
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34 | Sergi Consul-Pacareu, Jordi Albo-Canals, Xavier Vilasís-Cardona, Jordi Riera-Babures |
High performance DT-CNN camera device design on ACTEL IGLOO low power FPGA. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
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34 | Zair Abdelouahab, Slimane Hammoudi |
Concurrency in Object Oriented Language Actel. |
PDSE |
1997 |
DBLP DOI BibTeX RDF |
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34 | Zair Abdelouahab, Peter M. Dew |
Concurrency and Synchronisation in Actel. |
SBES |
1995 |
DBLP DOI BibTeX RDF |
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34 | Dennis McCarty |
System development using Actel field programmable gate arrays. |
Compcon |
1990 |
DBLP DOI BibTeX RDF |
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19 | Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle |
Radio frequency identification prototyping. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
low-power, RFID, prototyping, Design automation |
19 | Mohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi |
Design and Implementation of a 50MHZ DXT CoProcessor. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
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19 | René de Jesús Romero-Troncoso, Gilberto Herrera Ruiz |
FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
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19 | Maitrali Marik, Ajit Pal |
Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
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19 | D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar |
Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
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19 | Huiqun Liu, Kai Zhu 0001, D. F. Wong 0001 |
Circuit Partitioning with Complex Resource Constraints in FPGAs. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
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19 | Madhukar R. Korupolu, K. K. Lee, D. F. Wong 0001 |
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
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19 | Shashidhar Thakur, D. F. Wong 0001 |
Series-parallel functions and FPGA logic module design. |
ACM Trans. Design Autom. Electr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
series-parallel technology mapping, tree-based technology mapping algorithm, universal logic modules, field programmable gate arrays |
19 | Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi |
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
constant testability, FPGA, testing, manufacturing |
19 | Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri |
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture |
19 | Massoud Pedram, Bahman S. Nobandegani, Bryan Preas |
Design and analysis of segmented routing channels for row-based FPGA's. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
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19 | Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin |
Universal logic gate for FPGA design. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
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19 | Erik Brunvand |
Using FPGAs to implement self-timed systems. |
J. VLSI Signal Process. |
1993 |
DBLP DOI BibTeX RDF |
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