Search results for "Bitlines"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
70	Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic	Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines.	ISCA	2002	DBLP DOI BibTeX RDF	Dynamic Leakage Reduction
56	Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella	Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns.	HiPC	2006	DBLP DOI BibTeX RDF
55	Yen-Jen Chang, Feipei Lai	Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Dynamic zero-sensitivity, Bitlines, DZS, Cache, Power reduction
52	Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott	A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing.	MTDT	2003	DBLP DOI BibTeX RDF
38	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	A power-aware SWDR cell for reducing cache write power.	ISLPED	2003	DBLP DOI BibTeX RDF	circuit-level, write power, low power, cache, SRAM
33	Jeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu	Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines.	ICCD	2018	DBLP DOI BibTeX RDF
33	Khawar Sarfraz, Mansun Chan	A compact low-power 4-port register file with grounded write bitlines and single-ended read operations.	Integr.	2016	DBLP DOI BibTeX RDF
33	Khawar Sarfraz, Mansun Chan	A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines.	ESSCIRC	2015	DBLP DOI BibTeX RDF
33	Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure.	CICC	2013	DBLP DOI BibTeX RDF
33	Qi Li, Bo Wang 0020, Tony T. Kim	A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement.	ESSDERC	2012	DBLP DOI BibTeX RDF
33	Michael Wieckowski, Gregory K. Chen, Daeyeon Kim, David T. Blaauw, Dennis Sylvester	A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers.	ISQED	2011	DBLP DOI BibTeX RDF
33	Qi Li, Tony T. Kim	Analysis of SRAM hierarchical bitlines for optimal performance and variation tolerance.	ISOCC	2011	DBLP DOI BibTeX RDF
33	Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li 0001, Ken Mai, Lawrence T. Pileggi	Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines.	CICC	2008	DBLP DOI BibTeX RDF
33	Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn	Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density.	IEEE Trans. Circuits Syst. I Regul. Pap.	2006	DBLP DOI BibTeX RDF
33	Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Optimizing Leakage Energy Consumption in Cache Bitlines.	Des. Autom. Embed. Syst.	2004	DBLP DOI BibTeX RDF
19	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.	ISLPED	2010	DBLP DOI BibTeX RDF	sram
19	Wei Zhang 0032, Ki Chul Chun, Chris H. Kim	Variation aware performance analysis of gain cell embedded DRAMs.	ISLPED	2010	DBLP DOI BibTeX RDF	bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM
19	Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Rethinking DRAM design and organization for energy-constrained multi-cores.	ISCA	2010	DBLP DOI BibTeX RDF	chipkill, dram architecture, subarrays, energy-efficiency, locality
19	Sherif A. Tawfik, Volkan Kursun	Low power and robust 7T dual-Vt SRAM circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Mohammad Sharifkhani, Manoj Sachdev	Segmented Virtual Ground Architecture for Low-Power Embedded SRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
19	Peter Petrov, Alex Orailoglu	Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	software-controlled caching, Embedded systems, low-power, memory management, cache organization
19	Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li	The Design and Implementation of a Power Efficient Embedded SRAM.	PATMOS	2007	DBLP DOI BibTeX RDF
19	Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.	ISVLSI	2007	DBLP DOI BibTeX RDF
19	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
19	Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.	ISLPED	2006	DBLP DOI BibTeX RDF	data-bit reordering, low power SRAM, two-port SRAM, real-time image processing, majority logic
19	Kiran Puttaswamy, Gabriel H. Loh	Implementing Caches in a 3D Technology for High Performance Processors.	ICCD	2005	DBLP DOI BibTeX RDF
19	Peter Petrov, Daniel Tracy, Alex Orailoglu	Energy-effcient physically tagged caches for embedded processors with virtual memory.	DAC	2005	DBLP DOI BibTeX RDF
19	Peter Petrov, Alex Orailoglu	Tag compression for low power in dynamically customizable embedded processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Navid Azizi, Farid N. Najm, Andreas Moshovos	Low-leakage asymmetric-cell SRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
19	Peter Petrov, Alex Orailoglu	Virtual Page Tag Reduction for Low-power TLBs.	ICCD	2003	DBLP DOI BibTeX RDF
19	Peter Petrov, Alex Orailoglu	Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches.	DATE	2002	DBLP DOI BibTeX RDF
19	Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott	An Investigation into Crosstalk Noise in DRAM Structures.	MTDT	2002	DBLP DOI BibTeX RDF
19	Navid Azizi, Andreas Moshovos, Farid N. Najm	Low-leakage asymmetric-cell SRAM.	ISLPED	2002	DBLP DOI BibTeX RDF	low-leakage, low-power, SRAM, dual-Vt
19	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
19	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang	A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.	VLSI Design	2000	DBLP DOI BibTeX RDF
19	Rajiv V. Joshi, Wei Hwang	Design Considerations and Implementation of a High Performance Dynamic Register File.	VLSI Design	1999	DBLP DOI BibTeX RDF