Search results for "CML"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
131	Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera	A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.	ASP-DAC	2007	DBLP DOI BibTeX RDF	on-chip signaling circuit, impedance-unmatched CML driver, differential transmission-line, CML receiver, CML buffer, load resistance tuning, 10 Gbit/s, CMOS technology, power reduction, 90 nm
97	Yingbo Wang, Yali Wu, Andrew A. Allen, Barbara Espinoza, Peter J. Clarke, Yi Deng 0001	Towards the Operational Semantics of User-Centric Communication Models.	COMPSAC (1)	2009	DBLP DOI BibTeX RDF
91	Payam Heydari, Ravindran Mohanavelu	Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
91	Payam Heydari, Ravindran Mohanavelu	Design of ultra high-speed CMOS CML buffers and latches.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
91	William Ferreira 0001, Matthew Hennessy, Alan Jeffrey	A Theory of Weak Bisimulation for Core CML.	ICFP	1996	DBLP DOI BibTeX RDF
83	John H. Reppy, Claudio V. Russo, Yingqi Xiao	Parallel concurrent ML.	ICFP	2009	DBLP DOI BibTeX RDF	parallelism, concurrency, message passing
83	Payam Heydari	Design issues in low-voltage high-speed current-mode logic buffers.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	VLSI, noise, integrated circuit, high-speed, current-mode logic
83	Payam Heydari	Design and Analysis of Low-Voltage Current-Mode Logic Buffers.	ISQED	2003	DBLP DOI BibTeX RDF
81	André Ivanov, Vikram Devdas	Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	current mode logic (CML), CML circuit testing, bipolar circuit testing, catastrophic fault detection, defect-based testing
77	John H. Reppy, Yingqi Xiao	Specialization of CML message-passing primitives.	POPL	2007	DBLP DOI BibTeX RDF	static analysis, message passing, ML, concurrent languages
73	Yasmine Arafa, E. H. Mamdani	Scripting embodied agents behaviour with CML: character markup language.	IUI	2003	DBLP DOI BibTeX RDF	animated expression, automated animation scripting, mark-up languages, interface agents, embodied agents, CML, lifelike characters
73	Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst	Tools for the Characterization of Bipolar CML Testability.	VTS	2001	DBLP DOI BibTeX RDF	IFA, Automatic characterization, Fault-Modeling, CML
69	Ricky Robinson, Karen Henricksen, Jadwiga Indulska	XCML: A Runtime Representation for the Context Modelling Language.	PerCom Workshops	2007	DBLP DOI BibTeX RDF
69	Ahmed Bouajjani, Yan Jurski, Mihaela Sighireanu	A Generic Framework for Reasoning About Dynamic Networks of Infinite-State Processes.	TACAS	2007	DBLP DOI BibTeX RDF
63	Jadwiga Indulska, Ricky Robinson	Modelling Weiser's "Sal" Scenario with CML.	PerCom Workshops	2009	DBLP DOI BibTeX RDF
63	Sripriya R. Bandi, Clyde Washburn, P. R. Mukund, Jan Kolnik, Minxuan Liu, Ken Paradis, Steve Howard, Jeff Burleson	Accurate performance prediction of multi-GHz CML with data run-length variations.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
63	Michael M. Green, Ullas Singh	Design of CMOS CML circuits for high-speed broadband communications.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
63	Massimo Alioto, Gaetano Palumbo	Highly accurate and simple models for CML and ECL gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
63	Flemming Nielson, Hanne Riis Nielson	From CML to Process Algebras (Extended Abstract).	CONCUR	1993	DBLP DOI BibTeX RDF
56	Saghir A. Shaikh	IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver.	ITC	2004	DBLP DOI BibTeX RDF
51	Yasmine Arafa, Abe Mamdani	Multi-Modal Embodied Agents Scripting.	ICMI	2002	DBLP DOI BibTeX RDF	Mark-up Languages, Automated Animation Scripting, Animated Expression, MPEG-4, Embodied Agent, CML, Lifelike Characters
50	Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces.	ASP-DAC	2007	DBLP DOI BibTeX RDF	Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron
50	Elda Rossi, Andrew P. J. Emerson, Stefano Evangelisti	Common Data Format for Program Sharing and Integration.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF	Meta-systems, XML-CML, ab-initio methods, Local Orbitals, Globus, Grid Technology
49	Nader Kalantari, Michael M. Green	All-CMOS High-Speed CML Gates with Active Shunt-Peaking.	ISCAS	2007	DBLP DOI BibTeX RDF
49	Massimo Alioto, Gaetano Palumbo	Design techniques for low-power cascaded CML gates.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
49	Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham	Design For Testability Method for CML Digital Circuits.	DATE	1999	DBLP DOI BibTeX RDF
42	Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani	High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator.	ISCAS	2007	DBLP DOI BibTeX RDF
42	Peter Murray-Rust	Mathematics and Scientific Markup.	Calculemus/MKM	2007	DBLP DOI BibTeX RDF
42	Mingxiao Ding, Naigong Yu, Xiaogang Ruan	Cooperative Motor Learning Model for Cerebellar Control of Balance and Locomotion.	ISNN (1)	2006	DBLP DOI BibTeX RDF
42	John J. Leonard, Paul M. Newman, Richard J. Rikoski, José Neira, Juan D. Tardós	Towards Robust Data Association and Feature Modeling for Concurrent Mapping and Localization.	ISRR	2001	DBLP DOI BibTeX RDF
42	Hanne Riis Nielson, Flemming Nielson	Higher-Order Concurrent Programs with Finite Communication Topology.	POPL	1994	DBLP DOI BibTeX RDF
38	Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.	FPGA	2003	DBLP DOI BibTeX RDF	basic cell, FPGA, CML, SiGe
37	Bangli Liang, Tad A. Kwasniewski, Dianyong Chen	A 42-Gb/s Decision Circuit in 0.13µm CMOS.	CNSR	2008	DBLP DOI BibTeX RDF	CMOS CML, Shunt peaking, Split-resistor, Optical communication
35	David Rennie, Manoj Sachdev	Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
35	Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo	CML ring oscillators: oscillation frequency.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
35	Massimo Alioto, Gaetano Palumbo	Novel Simple Models Of Cml Propagation Delay.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
35	Hanne Riis Nielson, Torben Amtoft, Flemming Nielson	Behaviour Analysis and Safety Conditions: A Case Study in CML.	FASE	1998	DBLP DOI BibTeX RDF	formal program development, Embedded systems, program analysis
35	William Ferreira 0001, Matthew Hennessy	Towards a Semantic Theory of CML (Extended Abstract).	MFCS	1995	DBLP DOI BibTeX RDF
28	Guo-Jun Qi, Xian-Sheng Hua 0001, Yong Rui, Jinhui Tang 0001, Tao Mei 0001, Meng Wang 0001, Hong-Jiang Zhang	Correlative multilabel video annotation with temporal kernels.	ACM Trans. Multim. Comput. Commun. Appl.	2008	DBLP DOI BibTeX RDF	concept correlation, temporal kernel, Video annotation, multilabeling
28	Terrence J. Moore, Brian M. Sadler, Richard J. Kozick	Maximum-Likelihood Estimation, the Cramér-Rao Bound, and the Method of Scoring With Parameter Constraints.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
28	Minfen Shen, Lanxin Lin, Guoliang Chang	Novel Coupled Map Lattice Model for Prediction of EEG Signal.	ISNN (1)	2008	DBLP DOI BibTeX RDF	Couple Map Lattices, Normalized Radial Basis Function, EEG
28	Laura Effinger-Dean, Matthew Kehrt, Dan Grossman	Transactional events for ML.	ICFP	2008	DBLP DOI BibTeX RDF	synchronous message passing, transactional events, concurrency
28	Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu	A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Damian M. Lyons, Giselle R. Isner	Evaluation of a Parallel Architecture and Algorithm for Mapping and Localization.	CIRA	2007	DBLP DOI BibTeX RDF
28	Lukasz Ziarek, Philip Schatz, Suresh Jagannathan	Stabilizers: a modular checkpointing abstraction for concurrent functional programs.	ICFP	2006	DBLP DOI BibTeX RDF	transactions, checkpointing, concurrent programming, exception handling, error recovery, concurrent ML
28	Kouhei Hamaoka, Mitsuo Wada, Kosei Ishimura	Coupled Map Lattice Model based on Driving Strategy for City Traffic Simulation.	WSTST	2005	DBLP DOI BibTeX RDF
28	Steffen Müller 0001, Alexander Koenig, Horst-Michael Gross	Neural Architecture for Concurrent Map Building and Localization Using Adaptive Appearance Maps.	ICANN (2)	2005	DBLP DOI BibTeX RDF
28	David J. Johnston, Martin Fleury, Andy C. Downton	Prototyping Application Models in Concurrent ML.	Euro-Par	2003	DBLP DOI BibTeX RDF
28	Osvaldo Cairó, Julio César Alvarez	KAMET II: An Extended Knowledge-Acquisition Methodology.	KES	2003	DBLP DOI BibTeX RDF
28	Rosario Mita, Gaetano Palumbo	Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.	PATMOS	2002	DBLP DOI BibTeX RDF
28	Ryo Miyazaki, Satoru Yoshida, Tomoyuki Nishita, Yoshinori Dobashi	A Method for Modeling Clouds Based on Atmospheric Fluid Dynamics.	PG	2001	DBLP DOI BibTeX RDF	Coupled Map Lattice, simulation, Clouds, natural phenomena, cellular automaton, metaballs
28	Raikanta Sahu, Malcolm J. Panthaki, Walter H. Gerstle	An Object-Oriented Framework for Multidisciplinary, Multi-Physics, Computational Mechanics.	Eng. Comput.	1999	DBLP DOI BibTeX RDF	Analysis management, Computationalmechanics, Computational mechanics language
28	John F. McDonald 0001, Bryan S. Goda	Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
28	Brian N. Bershad, Dennis Lee 0001, Theodore H. Romer, J. Bradley Chen	Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches.	ASPLOS	1994	DBLP DOI BibTeX RDF
28	Derek C. Wong, Giovanni De Micheli, Michael J. Flynn	Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
24	Navin K. Ramamoorthy, Jayabharath Reddy M, Vishwanath Muniyappa	High Speed Serial Link Transmitter for 10Gig Ethernet Applications.	VLSI Design	2010	DBLP DOI BibTeX RDF	SerDes I/O, tap co-efficients, Gigabits per second(Gbps), Equalization, Transmitter, ISI, CML
24	Hans-Dieter Wohlmuth, Daniel Kehrer	A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS.	SBCCI	2004	DBLP DOI BibTeX RDF	flip-flop, pseudo random, CML
24	Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner	A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology.	ISLPED	2003	DBLP DOI BibTeX RDF	RF circuit, SOI CMOS, frequency divider, low power, CML
24	Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald 0001	A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	BC, BCII, FPGA, dynamic routing, CML
24	Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori	Rewritable Progammable Logic Array of Current Mode Logic.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Array logic, functional memory, logic-in-memory, associative memory, PLA, LSI, CML
23	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
22	Yoav Rubin, Shira Sohn, Pinhas Alpert	High-Resolution Humidity Observations Based on Commercial Microwave Links (CML) Data - Case of Tel Aviv Metropolitan Area.	Remote. Sens.	2023	DBLP DOI BibTeX RDF
22	Stefanie Scholz, Isabell Berns, Christian Winkler	Listen to the patients! Identifying CML patients' needs analyzing patient-generated content with AI-driven methodologies.	Frontiers Digit. Health	2023	DBLP DOI BibTeX RDF
22	Frederico S. Oliveira, Edresson Casanova, Arnaldo Cândido Júnior, Anderson da Silva Soares, Arlindo R. Galvão Filho	CML-TTS A Multilingual Dataset for Speech Synthesis in Low-Resource Languages.	CoRR	2023	DBLP DOI BibTeX RDF
22	Yiming Cui, Cheng Han, Dongfang Liu	CML-MOTS: Collaborative Multi-task Learning for Multi-Object Tracking and Segmentation.	CoRR	2023	DBLP DOI BibTeX RDF
22	Bruno Alberto Soares Oliveira, Giulia Zanon Castro, Giovanna Luiza Medina Ferreira, Frederico Gadelha Guimarães	CML-Cardio: a cascade machine learning model to predict cardiovascular disease risk as a primary prevention strategy.	Medical Biol. Eng. Comput.	2023	DBLP DOI BibTeX RDF
22	Yoav Rubin, Pinhas Alpert	Improved Calibration Method For CML Humidity Retrievals Over Complex Terrain.	ICASSP Workshops	2023	DBLP DOI BibTeX RDF
22	Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine	4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS.	ISOCC	2023	DBLP DOI BibTeX RDF
22	Pegah Golchin, Chengbo Zhou, Pratyush Agnihotri, Mehrdad Hajizadeh, Ralf Kundel, Ralf Steinmetz	CML-IDS: Enhancing Intrusion Detection in SDN Through Collaborative Machine Learning.	CNSM	2023	DBLP DOI BibTeX RDF
22	Frederico S. Oliveira, Edresson Casanova, Arnaldo Cândido Júnior, Anderson da Silva Soares, Arlindo R. Galvão Filho	CML-TTS: A Multilingual Dataset for Speech Synthesis in Low-Resource Languages.	TSD	2023	DBLP DOI BibTeX RDF
22	Yoav Rubin, Dorita Rostkier-Edelstein, Christian Chwala, Pinhas Alpert	Challenges in Diurnal Humidity Analysis from Cellular Microwave Links (CML) over Germany.	Remote. Sens.	2022	DBLP DOI BibTeX RDF
22	Dengjie Wang, Ziqiang Wang, Hao Xu, Jiawei Wang 0004, Zeliang Zhao, Chun Zhang, Zhihua Wang 0001, Hong Chen 0002	A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
22	Ethan Chou, Lorenzo Iotti, Ali M. Niknejad	Design of an Inductor-Less 72-GHz 2: 1 CMOS CML Frequency Divider With Dual-Core VCO.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
22	Roberto Nebuloni, Greta Cazzaniga, Michele d'Amico, Cristina Deidda, Carlo De Michele	Comparison of CML Rainfall Data against Rain Gauges and Disdrometers in a Mountainous Environment.	Sensors	2022	DBLP DOI BibTeX RDF
22	Varun Malik, Ruchi Mittal, Ajay Rana	BiCNN-CML: Hybrid Deep Learning Approach for Chronic Myeloid Leukemia.	IC3I	2022	DBLP DOI BibTeX RDF
22	Junfeng Tian, Yi Lu, Xianyu Zuo, Yang Liu 0055, Baojun Qiao, Minghu Fan, Qiang Ge, Sujuan Fan	A novel image encryption algorithm using PWLCM map-based CML chaotic system and dynamic DNA encryption.	Multim. Tools Appl.	2021	DBLP DOI BibTeX RDF
22	Hassan Dashtian, Dhiraj Murthy	CML-COVID: A Large-Scale COVID-19 Twitter Dataset with Latent Topics, Sentiment and Location Information.	CoRR	2021	DBLP BibTeX RDF
22	Thirumarai Selvi Chandraraju, J. Amudha 0001, R. Sudhakar 0001	A modified salp swarm algorithm (SSA) combined with a chaotic coupled map lattices (CML) approach for the secured encryption and compression of medical images during data transmission.	Biomed. Signal Process. Control.	2021	DBLP DOI BibTeX RDF
22	Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande, Mahendra Sakare	Design of a PRBS generator and a serializer using active inductor employed CML latch.	MWSCAS	2021	DBLP DOI BibTeX RDF
22	Youzhi Gu, Junkun Chen, Xiaolin Li, Yongzhen Chen, Jiangfeng Wu	A 32Gb/s NRZ Wireline Transmitter with CMFB- Based CML Driver in 28nm CMOS Technology.	MWSCAS	2021	DBLP DOI BibTeX RDF
22	Yi Yang 0006, Xiao Chen, Linhan Guo, Si Yu Huang, Wen Shu Xie, Wei Liu	Belief Reliability Analysis of Traffic Network: An Uncertain Percolation CML Model.	IEEM	2021	DBLP DOI BibTeX RDF
22	Jun Feng, Mohammadreza Beikmirza, Mohammadreza Mehrpoo, Leo C. N. de Vreede, Morteza S. Alavi	A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS.	ISOCC	2021	DBLP DOI BibTeX RDF
22	Hao Zhang 0061, Xiao-qing Wang, Xingyuan Wang 0001, Peng-fei Yan	Novel multiple images encryption algorithm using CML system and DNA encoding.	IET Image Process.	2020	DBLP DOI BibTeX RDF
22	Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar 0006, Gaurav Singh, Santosh Kumar Vishvakarma	A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
22	Susu Xu, Shijia Pan, Tong Yu 0001	CML-IOT 2020: the second workshop on continual and multimodal learning for internet of things.	UbiComp/ISWC Adjunct	2020	DBLP DOI BibTeX RDF
22	Maximiliano Cristiá, Diego A. Hollmann, Claudia S. Frydman	A multi-target compiler for CML-DEVS.	Simul.	2019	DBLP DOI BibTeX RDF
22	Xiaoteng Zhao, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins	A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
22	Chao Fan, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins	A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
22	Tong Yu 0001, Shijia Pan, Susu Xu, Yilin Shen, Botao Hao	CML-IOT 2019: the first workshop on continual and multimodal learning for internet of things.	UbiComp/ISWC Adjunct	2019	DBLP DOI BibTeX RDF
22	Mikko Hietanen, Janne Aikio, Alok Sethi, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen	Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI.	NORCAS	2019	DBLP DOI BibTeX RDF
22	Zoltán Tibenszky, Richard Achilles, Simon Buhr, Corrado Carta, Frank Ellinger	A Compact Inductorless 32 GHz Divide-by-2 CML Frequency Divider on 22 nm FD-SOI Technology.	ICECS	2019	DBLP DOI BibTeX RDF
22	Mohit Dua, Aishwarya Wesanekar, Vishwas Gupta, Mayank Bhola, Shelza Dua	Color Image Encryption using Synchronous CML-DNA and Weighted Bi-objective Genetic Algorithm.	BDIOT	2019	DBLP DOI BibTeX RDF
22	Jaime Cardenas, Abdul Khan, Li Chen 0001, Zhichao Zhang, Muhammad Khan	A Radiation-Tolerant CML Voltage Controlled Oscillator in 28nm CMOS FDSOI.	CCECE	2019	DBLP DOI BibTeX RDF
22	Xiangjun Wu, Kunshu Wang, Xingyuan Wang, Haibin Kan, Jürgen Kurths	Color image DNA encryption using NCA map-based CML and one-time keys.	Signal Process.	2018	DBLP DOI BibTeX RDF
22	Xingyuan Wang 0001, Yutao Hou, Shi-Bing Wang, Rui Li 0007	A New Image Encryption Algorithm Based on CML and DNA Sequence.	IEEE Access	2018	DBLP DOI BibTeX RDF
22	Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong	A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
22	Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine	A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion.	ICECS	2018	DBLP DOI BibTeX RDF
22	Asad Ali Nawaz, Jubaid Abdul Qayyum, Ahmet Cagri Ulusoy, John D. Cressler, Wibo D. Van Noort	A new figure-of-merit for CML gate delay estimation.	WiSNet	2018	DBLP DOI BibTeX RDF
22	Zhichao Zhang, Li Chen 0001, Hormoz Djahanshahi	A SEE Insensitive CML Voltage Controlled Oscillator in 65nm CMOS.	CCECE	2018	DBLP DOI BibTeX RDF
22	Masumeh Damghanian, Seyed Javad Azhari	A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications.	Integr.	2017	DBLP DOI BibTeX RDF