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Publication years (Num. hits)
1998-2007 (16) 2008-2013 (15) 2014-2019 (3)
Publication types (Num. hits)
article(13) inproceedings(21)
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Found 35 publication records. Showing 34 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
69Marko van Dooren, Eric Steegmans Combining the robustness of checked exceptions with the flexibility of unchecked exceptions using anchored exception declarations. Search on Bibsonomy OOPSLA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Cappuccino, anchored exception declaration, exception handling
37Mohammad Motamedi, Daniel D. Fong, Soheil Ghiasi Cappuccino: Efficient CNN Inference Software Synthesis for Mobile System-on-Chips. Search on Bibsonomy IEEE Embed. Syst. Lett. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
37Mohammad Motamedi, Daniel D. Fong, Soheil Ghiasi Cappuccino: Efficient Inference Software Synthesis for Mobile System-on-Chips. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
37Linhua Jiang, Hua Pan, Haibin Cai A New Model for Prediction of the Performance of a Cappuccino Pod. Search on Bibsonomy Int. J. Comput. Intell. Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
37Stewart M. McCauley, Morten H. Christiansen Learning Simple Statistics for Language Comprehension and Production: The CAPPUCCINO Model. Search on Bibsonomy CogSci The full citation details ... 2011 DBLP  BibTeX  RDF
37Frank Buddrus, Jörg Schödel Cappuccino - A C++ to Java translator. Search on Bibsonomy SAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Java, C++
36Luca Magnelli, Francesco A. Amoroso, Felice Crupi, Gregorio Cappuccino, Giuseppe Iannaccone Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo Design approach for high-bandwidth low-power three-stage operational amplifiers. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
36Francesco A. Amoroso, Andrea Pugliese 0002, Gregorio Cappuccino A new efficient SC integrator scheme for high-speed low-power applications. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
36Stephen Williams, Anita N. Vasavada, Jacques Nicolas Beneat, Gregorio Cappuccino, David C. Lin, Warren A. Rosen, M. Eric Carr, Kirk Reinkens, Mingrui Zhang, Francesco A. Amoroso Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students. Search on Bibsonomy FIE The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
36Francesco A. Amoroso, Andrea Pugliese 0002, Gregorio Cappuccino Design criterion for high-speed low-power SC circuits. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance. Search on Bibsonomy Microelectron. J. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582]. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo Settling Time Optimization for Three-Stage CMOS Amplifier Topologies. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Francesco A. Amoroso, Andrea Pugliese 0002, Gregorio Cappuccino Design considerations for fast-settling two-stage Miller-compensated operational amplifiers. Search on Bibsonomy ICECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino, Francesco A. Amoroso, Andrea Pugliese 0002 Class-AB output stage design for high-speed three-stage op-amps. Search on Bibsonomy ICECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances. Search on Bibsonomy ISCAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF CMOS analog integrated circuits, frequency compensation, operational amplifiers, transient response
36Davide Urbano, Emilio Arnieri, Gregorio Cappuccino, Giandomenico Amendola Integrated waveguides for ultra-high speed interconnects. Search on Bibsonomy Nano-Net The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo Settling Time Minimization of Operational Amplifiers. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo Design methodology of nested-Miller amplifiers for small capacitive loads. Search on Bibsonomy ECCTD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino, Andrea Pugliese 0002, Giuseppe Cocorullo Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. Search on Bibsonomy DSD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects. Search on Bibsonomy ICECS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino, Giuseppe Cocorullo Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino, Giuseppe Cocorullo CMOS sizing rule for high performance long interconnects. Search on Bibsonomy DATE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. Search on Bibsonomy ICECS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino Dynamic power of CMOS gates driving lossy transmission lines. Search on Bibsonomy ICECS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino, Giuseppe Cocorullo A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. Search on Bibsonomy EUROMICRO The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
36Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo High performance VLSI modules for division and square root. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
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