Search results for "Cappuccino"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
69	Marko van Dooren, Eric Steegmans	Combining the robustness of checked exceptions with the flexibility of unchecked exceptions using anchored exception declarations.	OOPSLA	2005	DBLP DOI BibTeX RDF	Cappuccino, anchored exception declaration, exception handling
37	Mohammad Motamedi, Daniel D. Fong, Soheil Ghiasi	Cappuccino: Efficient CNN Inference Software Synthesis for Mobile System-on-Chips.	IEEE Embed. Syst. Lett.	2019	DBLP DOI BibTeX RDF
37	Mohammad Motamedi, Daniel D. Fong, Soheil Ghiasi	Cappuccino: Efficient Inference Software Synthesis for Mobile System-on-Chips.	CoRR	2017	DBLP BibTeX RDF
37	Linhua Jiang, Hua Pan, Haibin Cai	A New Model for Prediction of the Performance of a Cappuccino Pod.	Int. J. Comput. Intell. Syst.	2013	DBLP DOI BibTeX RDF
37	Stewart M. McCauley, Morten H. Christiansen	Learning Simple Statistics for Language Comprehension and Production: The CAPPUCCINO Model.	CogSci	2011	DBLP BibTeX RDF
37	Frank Buddrus, Jörg Schödel	Cappuccino - A C++ to Java translator.	SAC	1998	DBLP DOI BibTeX RDF	Java, C++
36	Luca Magnelli, Francesco A. Amoroso, Felice Crupi, Gregorio Cappuccino, Giuseppe Iannaccone	Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.	Int. J. Circuit Theory Appl.	2014	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Design approach for high-bandwidth low-power three-stage operational amplifiers.	Int. J. Circuit Theory Appl.	2012	DBLP DOI BibTeX RDF
36	Francesco A. Amoroso, Andrea Pugliese 0002, Gregorio Cappuccino	A new efficient SC integrator scheme for high-speed low-power applications.	Int. J. Circuit Theory Appl.	2012	DBLP DOI BibTeX RDF
36	Stephen Williams, Anita N. Vasavada, Jacques Nicolas Beneat, Gregorio Cappuccino, David C. Lin, Warren A. Rosen, M. Eric Carr, Kirk Reinkens, Mingrui Zhang, Francesco A. Amoroso	Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students.	FIE	2012	DBLP DOI BibTeX RDF
36	Francesco A. Amoroso, Andrea Pugliese 0002, Gregorio Cappuccino	Design criterion for high-speed low-power SC circuits.	Int. J. Circuit Theory Appl.	2011	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582].	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Settling Time Optimization for Three-Stage CMOS Amplifier Topologies.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
36	Francesco A. Amoroso, Andrea Pugliese 0002, Gregorio Cappuccino	Design considerations for fast-settling two-stage Miller-compensated operational amplifiers.	ICECS	2009	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino, Francesco A. Amoroso, Andrea Pugliese 0002	Class-AB output stage design for high-speed three-stage op-amps.	ICECS	2009	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.	ISCAS	2009	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.	PATMOS	2008	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, frequency compensation, operational amplifiers, transient response
36	Davide Urbano, Emilio Arnieri, Gregorio Cappuccino, Giandomenico Amendola	Integrated waveguides for ultra-high speed interconnects.	Nano-Net	2007	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	Settling Time Minimization of Operational Amplifiers.	PATMOS	2007	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	Design methodology of nested-Miller amplifiers for small capacitive loads.	ECCTD	2007	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.	PATMOS	2006	DBLP DOI BibTeX RDF
36	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino, Andrea Pugliese 0002, Giuseppe Cocorullo	Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.	PATMOS	2005	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino	Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects.	DSD	2003	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino	Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects.	ICECS	2003	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino, Giuseppe Cocorullo	Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.	PATMOS	2002	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino, Giuseppe Cocorullo	CMOS sizing rule for high performance long interconnects.	DATE	2001	DBLP DOI BibTeX RDF
36	Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino	VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits.	ICECS	2001	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino	Dynamic power of CMOS gates driving lossy transmission lines.	ICECS	2001	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino, Giuseppe Cocorullo	A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.	EUROMICRO	1999	DBLP DOI BibTeX RDF
36	Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo	High performance VLSI modules for division and square root.	Microprocess. Microsystems	1998	DBLP DOI BibTeX RDF