Search results for "Carry-save-addition"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
93	Mike Paterson, Nicholas Pippenger, Uri Zwick	Faster Circuits and Shorter Formulae for Multiple Addition, Multiplication and Symmetric Boolean Functions	FOCS	1990	DBLP DOI BibTeX RDF	multiplication circuits, multiple addition, shallowest possible circuits, shortest possible formulas, occurrence matrix, shortest multiple carry-save addition formulas, delay matrix, multiple carry-save adders, multiplication, symmetric Boolean functions, carry-save addition
75	Viktor Bunimov, Manfred Schimmler	Area and Time Efficient Modular Multiplication of Large Integers.	ASAP	2003	DBLP DOI BibTeX RDF	Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition
74	Mark A. Erle, Michael J. Schulte	Decimal Multiplication Via Carry-Save Addition.	ASAP	2003	DBLP DOI BibTeX RDF
59	Viktor Bunimov, Manfred Schimmler	Efficient Parallel Multiplication Algorithm for Large Integres.	Euro-Par	2003	DBLP DOI BibTeX RDF	large number arithmetic, redundant numbers, Computer arithmetic, integer multiplication, carry save addition, parallel multiplication
56	Mark A. Erle, Michael J. Schulte, Brian J. Hickmann	Decimal Floating-Point Multiplication Via Carry-Save Addition.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
47	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	Improved Design of High-Performance Parallel Decimal Multipliers.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Decimal multiplication, decimal carry-save addition, decimal codings, parallel multiplication
47	Dhananjay S. Phatak, Tom Goff, Israel Koren	Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	constant-time addition, simultaneous format conversion, redundant adders, signed-digit addition, 4:2 compressor, Redundant representations, carry-save addition
47	Junhyung Um, Taewhan Kim	An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	VLSI, arithmetic circuits, Carry-save-addition
47	R. Gnanasekaran	On a Bit-Serial Input and Bit-Serial Output Multiplier.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition
47	John H. Zurawski, J. B. Gosling	Design of High-Speed Digital Divider Units.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	uncommitted logic arrays (gate arrays), Borrow?save subtraction, carry?save addition, digital division, group subtractor, iterative division, digital arithmetic
44	Oleg Mazonka, Eduardo Chielle, Deepraj Soni, Michail Maniatakos	Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition.	ICCAD	2022	DBLP DOI BibTeX RDF
44	Daniel Dinu, Johann Großschädl, Yann Le Corre	Efficient Masking of ARX-Based Block Ciphers Using Carry-Save Addition on Boolean Shares.	ISC	2017	DBLP DOI BibTeX RDF
39	Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin	A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Junhyung Um, Taewhan Kim, C. L. Liu 0001	A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.	DAC	2000	DBLP DOI BibTeX RDF
27	Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin	A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma	A multiplication-accumulation computation unit with optimized compressors and minimized switching activities.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
16	Shugang Wei, Kensuke Shimizu	Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
12	Ismo Hänninen, Jarmo Takala	Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata.	SAMOS	2009	DBLP DOI BibTeX RDF	nanotechnology, multiplication, arithmetic, QCA
12	Mohamed Anane, Hamid Bessalah, Mohamed Issad, Nadjia Anane, Hassen Salhi	Higher Radix and Redundancy Factor for Floating Point SRT Division.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
12	Jun-Hong Chen, Wen-Ching Lin, Hao-Hsuan Wu, Ming-Der Shieh	High-speed modular multiplication design for public-key cryptosystems.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Ramachandruni Venkata Kamala, M. B. Srinivas	High-Throughput Montgomery Modular Multiplication.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
12	Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas	An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n).	DSD	2006	DBLP DOI BibTeX RDF
12	Eric Rice, Richard Hughey	A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF	hardware division, linear convergence, Computer arithmetic, prescaling