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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 23 occurrences of 15 keywords
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Results
Found 23 publication records. Showing 23 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
93 | Mike Paterson, Nicholas Pippenger, Uri Zwick |
Faster Circuits and Shorter Formulae for Multiple Addition, Multiplication and Symmetric Boolean Functions ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 31st Annual Symposium on Foundations of Computer Science, St. Louis, Missouri, USA, October 22-24, 1990, Volume II, pp. 642-650, 1990, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
multiplication circuits, multiple addition, shallowest possible circuits, shortest possible formulas, occurrence matrix, shortest multiple carry-save addition formulas, delay matrix, multiple carry-save adders, multiplication, symmetric Boolean functions, carry-save addition |
75 | Viktor Bunimov, Manfred Schimmler |
Area and Time Efficient Modular Multiplication of Large Integers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 400-, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition |
74 | Mark A. Erle, Michael J. Schulte |
Decimal Multiplication Via Carry-Save Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 348-, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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59 | Viktor Bunimov, Manfred Schimmler |
Efficient Parallel Multiplication Algorithm for Large Integres. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2003. Parallel Processing, 9th International Euro-Par Conference, Klagenfurt, Austria, August 26-29, 2003. Proceedings, pp. 923-928, 2003, Springer, 3-540-40788-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
large number arithmetic, redundant numbers, Computer arithmetic, integer multiplication, carry save addition, parallel multiplication |
56 | Mark A. Erle, Michael J. Schulte, Brian J. Hickmann |
Decimal Floating-Point Multiplication Via Carry-Save Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 46-55, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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47 | Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi |
Improved Design of High-Performance Parallel Decimal Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(5), pp. 679-693, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Decimal multiplication, decimal carry-save addition, decimal codings, parallel multiplication |
47 | Dhananjay S. Phatak, Tom Goff, Israel Koren |
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1267-1278, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
constant-time addition, simultaneous format conversion, redundant adders, signed-digit addition, 4:2 compressor, Redundant representations, carry-save addition |
47 | Junhyung Um, Taewhan Kim |
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(3), pp. 215-233, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
VLSI, arithmetic circuits, Carry-save-addition |
47 | R. Gnanasekaran |
On a Bit-Serial Input and Bit-Serial Output Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(9), pp. 878-880, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition |
47 | John H. Zurawski, J. B. Gosling |
Design of High-Speed Digital Divider Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(9), pp. 691-699, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
uncommitted logic arrays (gate arrays), Borrow?save subtraction, carry?save addition, digital division, group subtractor, iterative division, digital arithmetic |
44 | Oleg Mazonka, Eduardo Chielle, Deepraj Soni, Michail Maniatakos |
Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022, pp. 99:1-99:9, 2022, ACM, 978-1-4503-9217-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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44 | Daniel Dinu, Johann Großschädl, Yann Le Corre |
Efficient Masking of ARX-Based Block Ciphers Using Carry-Save Addition on Boolean Shares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security - 20th International Conference, ISC 2017, Ho Chi Minh City, Vietnam, November 22-24, 2017, Proceedings, pp. 39-57, 2017, Springer, 978-3-319-69658-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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39 | Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin |
A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3780-3783, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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36 | Junhyung Um, Taewhan Kim, C. L. Liu 0001 |
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 98-103, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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27 | Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin |
A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1151-1161, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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17 | Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma |
A multiplication-accumulation computation unit with optimized compressors and minimized switching activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 6118-6121, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Shugang Wei, Kensuke Shimizu |
Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 221-224, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Ismo Hänninen, Jarmo Takala |
Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 118-127, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
nanotechnology, multiplication, arithmetic, QCA |
12 | Mohamed Anane, Hamid Bessalah, Mohamed Issad, Nadjia Anane, Hassen Salhi |
Higher Radix and Redundancy Factor for Floating Point SRT Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(6), pp. 774-779, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Jun-Hong Chen, Wen-Ching Lin, Hao-Hsuan Wu, Ming-Der Shieh |
High-speed modular multiplication design for public-key cryptosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 680-683, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Ramachandruni Venkata Kamala, M. B. Srinivas |
High-Throughput Montgomery Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 58-62, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas |
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 155-159, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Eric Rice, Richard Hughey |
A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 54-62, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hardware division, linear convergence, Computer arithmetic, prescaling |
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