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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 23 occurrences of 20 keywords
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Results
Found 25 publication records. Showing 25 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | Jack W. Davidson, Richard A. Vaughan |
The Effect of Instruction Set Complexity on Program Size and Memory Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 60-64, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
26 | David Ryan Koes, Seth Copen Goldstein |
Near-optimal instruction selection on dags. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 45-54, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
instruction selection |
23 | Gabriel M. Silberman, Kemal Ebcioglu |
An architectural framework for migration from CISC to higher performance platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 6th international conference on Supercomputing, ICS 1992, Washington, DC, USA, July 19-24, 1992, pp. 198-215, 1992, ACM, 0-89791-485-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Kevin J. McNeley, Veljko M. Milutinovic |
Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 7(1), pp. 60-72, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 |
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Siddharth Rele, Vipin Jain, Santosh Pande, J. Ramanujam |
Compact and efficient code generation through program restructuringon limited memory embedded DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4), pp. 477-494, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Anjali Mahajan, M. Sadique Ali |
Superblock scheduling using genetic programming for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE ICCI ![In: Proceedings of the Seventh IEEE International Conference on Cognitive Informatics, ICCI 2008, Stanford University, California, USA, August 14-16, 2008, pp. 261-266, 2008, IEEE Computer Society, 978-1-4244-2538-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung |
Customization of a CISC Processor Core for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 152-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
CISC-processor, Complex-instruction, ROM-compile, Low-power-design, Microcode |
15 | Kuo-Su Hsiao, Chung-Ho Chen |
An efficient wakeup design for energy reduction in high-performance superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 353-360, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
issue window, wakeup logic, low power, high performance |
14 | Yuzhou Huang, Liangbin Xie, Xintao Wang, Ziyang Yuan, Xiaodong Cun, Yixiao Ge, Jiantao Zhou 0001, Chao Dong, Rui Huang, Ruimao Zhang, Ying Shan |
SmartEdit: Exploring Complex Instruction-based Image Editing with Multimodal Large Language Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2312.06739, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal |
Automatic complex instruction identification for efficient application mapping onto ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, February 25-28, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Armita Peymandoust, Tajana Simunic, Giovanni De Micheli |
Complex instruction and software library mapping for embedded software using symbolic algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8), pp. 964-975, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | David R. Stiles, Harold L. McFarland |
Pipeline control for a single cycle VLSI implementation of a complex instruction set computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPCON ![In: Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, COMPCON Spring 89, San Francisco, CA, USA, February 27 - March 3, 1989, Digest of Papers., pp. 504-508, 1989, IEEE Computer Society, 0-8186-1909-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
14 | Michael J. Flynn, Chad L. Mitchell, Johannes M. Mulder |
And Now a Case for More Complex Instruction Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 20(9), pp. 71-83, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
14 | Richard L. Norton, Jacob A. Abraham |
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, pp. 277-282, 1983, ACM, 0-89791-101-6. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
|
14 | Pedro Furtado 0001, Henrique Madeira |
Fault Injection Evaluation of Assigned Signatures in a RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings, pp. 55-72, 1996, Springer, 3-540-61772-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
11 | Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster 0001 |
Reducing power while increasing performance with supercisc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(3), pp. 658-686, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Low-power, synthesis, VLIW, predication, multicore architectures |
11 | Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami |
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 25-27 June 2001, Monterey, CA, USA, pp. 50-57, 2001, IEEE Computer Society, 0-7695-1206-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Partha Biswas, Nikil D. Dutt |
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(10), pp. 1216-1226, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction |
10 | Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta |
Dynamic Optimization of Micro-Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, pp. 165-176, 2003, IEEE Computer Society, 0-7695-1871-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Partha Biswas, Nikil D. Dutt |
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 104-112, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment |
10 | Uming Ko, Poras T. Balsara, Ashwini K. Nanda |
Energy optimization of multilevel cache architectures for RISC and CISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 299-308, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Shailesh Sutarwala, Pierre G. Paulin |
Flexible modeling environment for embedded systems design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Third International Workshop on Hardware/Software Codesign, CODES 1994, Grenoble, France, September 22-24, 1994, pp. 124-130, 1994, IEEE Computer Society, 0-8186-6315-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
6 | Todd A. Proebsting |
BURS Automata Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 17(3), pp. 461-486, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
code-generator generator, dynamic programming, code generation, tree pattern matching |
6 | Yashwant K. Malaiya, Sheng Feng |
Design of a testable RISC-to-CISC control architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988, pp. 57-59, 1988, ACM/IEEE, 0-8186-1919-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
RISC |
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