Search results for "DDECS"

Hits ?▲	Authors	Title	Venue	Year	Link
75	Alejandro Nocua, Said Derradji, Gregory Vaumourin, Pierre-Axel Lagadec, Zoltan Menyhart	Mont-Blanc 2020: Simulation Efforts Towards Exascale High Performance Computing : Embedded Tutorial on "DDECS-2020".	DDECS	2020	DBLP DOI BibTeX RDF
75		Foreword to the 16th IEEE DDECS Symposium.	DDECS	2013	DBLP DOI BibTeX RDF
45	Maksim Jenihhin, Hana Kubátová, Nele Metens, Jaan Raik, Foisal Ahmed, Jan Belohoubek (eds.)	26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023	DDECS	2023	DBLP DOI BibTeX RDF
45	Jonas Bertels, Michiel Van Beirendonck, Furkan Turan, Ingrid Verbauwhede	Hardware Acceleration of FHEW.	DDECS	2023	DBLP DOI BibTeX RDF
45	Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik	APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors.	DDECS	2023	DBLP DOI BibTeX RDF
45	Christian Fibich, Martin Horauer, Roman Obermaisser	Characterization of Interconnect Fault Effects in SRAM-based FPGAs.	DDECS	2023	DBLP DOI BibTeX RDF
45	Maryam Saadat-Safa, Tahoura Mosavirik, Shahin Tajik	Counterfeit Chip Detection using Scattering Parameter Analysis.	DDECS	2023	DBLP DOI BibTeX RDF
45	Luigi Capogrosso, Federico Cunico, Michele Lora, Marco Cristani, Franco Fummi, Davide Quaglia	Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications.	DDECS	2023	DBLP DOI BibTeX RDF
45	Sergio Vinagrero Gutierrez, Pietro Inglese, Giorgio Di Natale, Elena Ioana Vatajelu	Open Automation Framework for Complex Parametric Electrical Simulations.	DDECS	2023	DBLP DOI BibTeX RDF
45	Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic	Active Wire Fences for Multitenant FPGAs.	DDECS	2023	DBLP DOI BibTeX RDF
45	Mohamed El Bouazzati, Russell Tessier, Philippe A. Tanguy, Guy Gogniat	A Lightweight Intrusion Detection System against IoT Memory Corruption Attacks.	DDECS	2023	DBLP DOI BibTeX RDF
45	Rune Krauss, Mehran Goli, Rolf Drechsler	Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes.	DDECS	2023	DBLP DOI BibTeX RDF
45	Robert Hülle, Petr Fiser, Jan Schmidt	Reducing Output Response Aliasing Using Boolean Optimization Techniques.	DDECS	2023	DBLP DOI BibTeX RDF
45	Eleonora Vacca, Sarah Azimi, Luca Sterpone	A Comprehensive Analysis of Transient Errors on Systolic Arrays.	DDECS	2023	DBLP DOI BibTeX RDF
45	Luigi Capogrosso, Luca Geretti, Marco Cristani, Franco Fummi, Tiziano Villa	HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package.	DDECS	2023	DBLP DOI BibTeX RDF
45	Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina	MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers.	DDECS	2023	DBLP DOI BibTeX RDF
45	Fabio A. Velarde Gonzalez, Lukas Hahne, Katrin Ortstein, André Lange, Sonja Crocoll	Supporting analog design for reliability by efficient provision of reliability information to designers.	DDECS	2023	DBLP DOI BibTeX RDF
45	Michal Pinos, Vojtech Mrazek, Lukás Sekanina	Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits.	DDECS	2023	DBLP DOI BibTeX RDF
45	Nicolas Gerlin, Endri Kaja, Fabian Vargas 0001, Li Lu, Anselm Breitenreiter, Junchao Chen 0001, Markus Ulbricht 0002, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker	Bits, Flips and RISCs.	DDECS	2023	DBLP DOI BibTeX RDF
45	Paolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Vincenzo Tancorre	Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults.	DDECS	2023	DBLP DOI BibTeX RDF
45	Joseline Heuer, Rene Krenz-Baath, Roman Obermaisser	Verifying Bio-Electronic Systems.	DDECS	2023	DBLP DOI BibTeX RDF
45	Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda	A Reliability-aware Environment for Design Exploration for GPU Devices.	DDECS	2023	DBLP DOI BibTeX RDF
45	Dominic Korner, Andreas Kramer, Klaus Hofmann, Felix Hausch	Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates.	DDECS	2023	DBLP DOI BibTeX RDF
45	Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez 0001, Alberto Bosio	Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator.	DDECS	2023	DBLP DOI BibTeX RDF
45	Elias Trommer, Bernd Waschneck, Akash Kumar 0001	High-Throughput Approximate Multiplication Models in PyTorch.	DDECS	2023	DBLP DOI BibTeX RDF
45	Letícia Maria Veiras Bolzani	Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing?	DDECS	2023	DBLP DOI BibTeX RDF
45	Vojtech Mrazek	Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial).	DDECS	2023	DBLP DOI BibTeX RDF
45	Zahra Hojati, Zainalabedin Navabi	A Low-Cost Combinational Approximate Multiplier.	DDECS	2023	DBLP DOI BibTeX RDF
45	Jure Vreca, Anton Biasizzo	A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel.	DDECS	2023	DBLP DOI BibTeX RDF
45	Ali Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Masoud Daneshtalab	NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures.	DDECS	2023	DBLP DOI BibTeX RDF
45	Swantje Plambeck, Görschwin Fey	Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models.	DDECS	2023	DBLP DOI BibTeX RDF
45	Daniel Öhlinger, Ulrich Schmid 0001	A Digital Delay Model Supporting Large Adversarial Delay Variations.	DDECS	2023	DBLP DOI BibTeX RDF
45	Marcel Merten, Muhammad Hassan 0002, Rolf Drechsler	Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques.	DDECS	2023	DBLP DOI BibTeX RDF
45	Nooshin Nosrati, Zainalabedin Navabi	A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators.	DDECS	2023	DBLP DOI BibTeX RDF
45	Carl Riehm, Christoph Frisch, Florin Burcea, Matthias Hiller, Michael Pehl, Ralf Brederlow	Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations.	DDECS	2023	DBLP DOI BibTeX RDF
45	Khakim Akhunov, Kasim Sinan Yildirim	LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory Computing.	DDECS	2023	DBLP DOI BibTeX RDF
45	Michal Kekely, Jan Korenek	Optimizing Packet Classification on FPGA.	DDECS	2023	DBLP DOI BibTeX RDF
45	Adebayo Omotosho, Sirine IIahi, Ernesto Cristopher Villegas Castillo, Christian Hammer 0001, Christian Sauer 0001	Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype.	DDECS	2023	DBLP DOI BibTeX RDF
45		25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022	DDECS	2022	DBLP DOI BibTeX RDF
45	Roshwin Sengupta, Ilia Polian, John P. Hayes	Stochastic Computing Architectures for Lightweight LSTM Neural Networks.	DDECS	2022	DBLP DOI BibTeX RDF
45	Jan Klhufek, Vojtech Mrazek	ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators.	DDECS	2022	DBLP DOI BibTeX RDF
45	Matús Oleksák, Vojtech Miskovský	Correlation Power Analysis of SipHash.	DDECS	2022	DBLP DOI BibTeX RDF
45	Milan Funck, Vladimir Herdt, Rolf Drechsler	Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions.	DDECS	2022	DBLP DOI BibTeX RDF
45	Owen Hoffend, John P. Hayes	Analyzing Multilevel Stochastic Circuits using Correlation Matrices.	DDECS	2022	DBLP DOI BibTeX RDF
45	Salah Daddinounou, Elena Ioana Vatajelu	Synaptic Control for Hardware Implementation of Spike Timing Dependent Plasticity.	DDECS	2022	DBLP DOI BibTeX RDF
45	Levent Aksoy, Alexander Hepp, Johanna Baehr, Samuel Pagliarini	Hardware Obfuscation of Digital FIR Filters.	DDECS	2022	DBLP DOI BibTeX RDF
45	Antonios Banos, Yannick Verbelen, Suresh Kaluvan, Chris Hutson, Matthew Ryan Tucker, Tom B. Scott 0001	Hexapod robotic system for indoor neutron and gamma radiation mapping and inspection.	DDECS	2022	DBLP DOI BibTeX RDF
45	Christopher A. Metz, Mehran Goli, Rolf Drechsler	ML-based Power Estimation of Convolutional Neural Networks on GPGPUs.	DDECS	2022	DBLP DOI BibTeX RDF
45	Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari	Functional Verification of Arithmetic Circuits: Survey of Formal Methods.	DDECS	2022	DBLP DOI BibTeX RDF
45	Gerold Fink, Medina Hamidovic, Werner Haselmayr, Robert Wille	A Concept Towards Pressure-Controlled Microfluidic Networks.	DDECS	2022	DBLP DOI BibTeX RDF
45	Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola	A Design Space Exploration Framework for Memristor-Based Crossbar Architecture.	DDECS	2022	DBLP DOI BibTeX RDF
45	Zaheer Tabassam, Syed Rameez Naqvi, Andreas Steininger	AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages.	DDECS	2022	DBLP DOI BibTeX RDF
45	Weiyan Zhang, Mehran Goli, Rolf Drechsler	Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression.	DDECS	2022	DBLP DOI BibTeX RDF
45	Kemal Çaglar Coskun, Muhammad Hassan 0002, Rolf Drechsler	Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters.	DDECS	2022	DBLP DOI BibTeX RDF
45	Richard Ravasz, Adam Hudec, Daniel Arbet, Viera Stopjaková	On-Chip Current Sensing Approaches for DC-DC Converters.	DDECS	2022	DBLP DOI BibTeX RDF
45	Patrick Karl, Tim Fritzmann, Georg Sigl	Hardware Accelerated FrodoKEM on RISC-V.	DDECS	2022	DBLP DOI BibTeX RDF
45	David Maljar, Daniel Arbet, Martin Kovác, Róbert Ondica, Viera Stopjaková	Autocalibration Approach for Improving Robustness of Analog ICs.	DDECS	2022	DBLP DOI BibTeX RDF
45	Rolf Drechsler, Alireza Mahzoon, Mehran Goli	Towards Polynomial Formal Verification of Complex Arithmetic Circuits.	DDECS	2022	DBLP DOI BibTeX RDF
45	Alessandro Veronesi, Francesco Dall'Occo, Davide Bertozzi, Michele Favalli, Milos Krstic	Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study.	DDECS	2022	DBLP DOI BibTeX RDF
45	Josef Strnadel	Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking.	DDECS	2022	DBLP DOI BibTeX RDF
45	Troya Çagil Köylü, Luíza C. Garaffa, Cezar Reinbrecht, Mahdi Zahedi, Said Hamdioui, Mottaqiallah Taouil	Exploiting PUF Variation to Detect Fault Injection Attacks.	DDECS	2022	DBLP DOI BibTeX RDF
45	Yannick Verbelen, Antonios Banos, Tom B. Scott 0001	Fault Tolerant Synchronous Multi-Channel Buck Converter for Nuclear Inspection Instruments.	DDECS	2022	DBLP DOI BibTeX RDF
45	Ashton Snelgrove, Pierre-Emmanuel Gaillardon	Programmable logic elements using multigate ambipolar transistors.	DDECS	2022	DBLP DOI BibTeX RDF
45	Noura Ait Manssour, Vianney Lapôtre, Guy Gogniat, Arnaud Tisserand	Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks.	DDECS	2022	DBLP DOI BibTeX RDF
45	Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena Ioana Vatajelu	Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?	DDECS	2022	DBLP DOI BibTeX RDF
45	Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale	On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors.	DDECS	2022	DBLP DOI BibTeX RDF
45	Annachiara Ruospo, Gabriele Gavarini, Ilaria Bragaglia, Marcello Traiola, Alberto Bosio, Ernesto Sánchez 0001	Selective Hardening of Critical Neurons in Deep Neural Networks.	DDECS	2022	DBLP DOI BibTeX RDF
45	Florian Huemer, Robert Najvirt, Andreas Steininger	On SAT-Based Model Checking of Speed-Independent Circuits.	DDECS	2022	DBLP DOI BibTeX RDF
45	Vít Masek, Martin Novotný	Versatile Hardware Framework for Elliptic Curve Cryptography.	DDECS	2022	DBLP DOI BibTeX RDF
45	Muhammad Shafique 0001, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek (eds.)	24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021	DDECS	2021	DBLP DOI BibTeX RDF
45	Hassan Ebrahimi, Hans G. Kerkhoff	Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level.	DDECS	2021	DBLP DOI BibTeX RDF
45	Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sánchez 0001, Giovanni Squillero	A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores.	DDECS	2021	DBLP DOI BibTeX RDF
45	Siang-Yun Lee, Heinz Riener, Giovanni De Micheli	Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.	DDECS	2021	DBLP DOI BibTeX RDF
45	Lukasz A. Kadlubowski, Piotr Kmon	Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array.	DDECS	2021	DBLP DOI BibTeX RDF
45	Alija Dervic, Saman Kohneh Poushi, Horst Zimmermann	Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nm.	DDECS	2021	DBLP DOI BibTeX RDF
45	Alberto Bosio, Mayeul Cantan, Cédric Marchand 0002, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola	Emerging Technologies: Challenges and Opportunities for Logic Synthesis.	DDECS	2021	DBLP DOI BibTeX RDF
45	Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik	CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector.	DDECS	2021	DBLP DOI BibTeX RDF
45	Alessandro Savino, Marcello Traiola, Stefano Di Carlo, Alberto Bosio	Efficient Neural Network Approximation via Bayesian Reasoning.	DDECS	2021	DBLP DOI BibTeX RDF
45	David Maljar, Michal Sovcík, Daniel Arbet, Viera Stopjaková	Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration.	DDECS	2021	DBLP DOI BibTeX RDF
45	Davide Appello, Paolo Bernardi, Andrea Calabrese, Stefano Littardi, Giorgio Pollaccia, Stefano Quer, Vincenzo Tancorre, Roberto Ugioli	Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures.	DDECS	2021	DBLP DOI BibTeX RDF
45	Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda	On the Functional Test of Special Function Units in GPUs.	DDECS	2021	DBLP DOI BibTeX RDF
45	Roman Vrána, Jan Korenek	Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis.	DDECS	2021	DBLP DOI BibTeX RDF
45	Zdenek Vasícek	Synthesis of approximate circuits for LUT-based FPGAs.	DDECS	2021	DBLP DOI BibTeX RDF
45	Mitko Veleski, Michael Hübner 0001, Milos Krstic, Rolf Kraemer	Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation.	DDECS	2021	DBLP DOI BibTeX RDF
45	Nurettin Bölücü, Suleyman Tosun	Q-Learning-based Routing Algorithm for 3D Network-on-Chips.	DDECS	2021	DBLP DOI BibTeX RDF
45	Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková	EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design.	DDECS	2021	DBLP DOI BibTeX RDF
45	Raghda El Shehaby, Andreas Steininger	Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines.	DDECS	2021	DBLP DOI BibTeX RDF
45	Malik Imran, Zain Ul Abideen 0002, Samuel Pagliarini	An Open-source Library of Large Integer Polynomial Multipliers.	DDECS	2021	DBLP DOI BibTeX RDF
45	Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, André Alberts, Franco Fummi	Predictive Fault Grouping based on Faulty AC Matrices.	DDECS	2021	DBLP DOI BibTeX RDF
45	Olivier Sentieys, Silviu-Ioan Filip, David Briand, David Novo, Etienne Dupuis, Ian O'Connor, Alberto Bosio	AdequateDL: Approximating Deep Learning Accelerators.	DDECS	2021	DBLP DOI BibTeX RDF
45	Michal Orsák, Tomás Benes	High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories.	DDECS	2021	DBLP DOI BibTeX RDF
45	Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez 0001, Luigi Dilillo	A Model-Based Framework to Assess the Reliability of Safety-Critical Applications.	DDECS	2021	DBLP DOI BibTeX RDF
45	Jianan Wen, Markus Ulbricht 0002, Eduardo Perez, Xin Fan 0003, Milos Krstic	Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment.	DDECS	2021	DBLP DOI BibTeX RDF
45	Pawel Skrzypiec, Robert Szczygiel	Development of On-Chip Calibration for Hybrid Pixel Detectors.	DDECS	2021	DBLP DOI BibTeX RDF
45	Denis Dutey, Stephane Martin, Anne Merlande, Om Ranjan	Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional Tests.	DDECS	2021	DBLP DOI BibTeX RDF
45	Rolf Drechsler	PolyAdd: Polynomial Formal Verification of Adder Circuits.	DDECS	2021	DBLP DOI BibTeX RDF
45	Zoran Stamenkovic, Hassen Aziza, Ernesto Sánchez 0001, Alberto Bosio	Tutorial: Silicon Systems for Wireless LAN.	DDECS	2021	DBLP DOI BibTeX RDF
45	Martin Skriver, Anders Stengaard Sørensen, Ulrik Pagh Schultz	HEIST: A Hardware Signal Fault Injection Methodology Enabling Feasible Software Robustness Testing.	DDECS	2021	DBLP DOI BibTeX RDF
45	Christoph Niemann 0002, Michael Rethfeldt, Dirk Timmermann	Approximate Multipliers for Optimal Utilization of FPGA Resources.	DDECS	2021	DBLP DOI BibTeX RDF
45	Vukan D. Damnjanovic, Marija L. Petrovic, Vladimir M. Milovanovic	A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis.	DDECS	2021	DBLP DOI BibTeX RDF