Search results for "DFY"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
85	Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai	DFM/DFY practices during physical designs for timing, signal integrity, and power.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
77	Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki	DFM/DFY: should you trust the surgeon or the family doctor?	DATE	2007	DBLP DOI BibTeX RDF
52	Jamil Kawa, Charles C. Chiang	DFM issues for 65nm and beyond.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	DFY, DFM
33	Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl	Robust wiring networks for DfY considering timing constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	redundant wiring, timing constraint aware, open defects, design for yield
33	Srikanth Venkataraman	DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield.	ISQED	2007	DBLP DOI BibTeX RDF
33	Rajesh Raina	What is DFM & DFY and Why Should I Care ?	ITC	2006	DBLP DOI BibTeX RDF
33	Robert C. Aitken	The Design and Validation of IP for DFM/DFY Assurance.	ITC	2006	DBLP DOI BibTeX RDF
33	R. Scott Fetherston	DFT, DFY, DFR: Who Cares?	ITC	1999	DBLP DOI BibTeX RDF
33	James A. Monzel	DFT, DFY, and DFR; Which One(s) Do You Worry About?	ITC	1999	DBLP DOI BibTeX RDF
33	David M. Wu	"DFY and DFR are more important than DFT".	ITC	1999	DBLP DOI BibTeX RDF
33	Robert C. Aitken	It Makes Sense to Combine DFT and DFR/DFY.	ITC	1999	DBLP DOI BibTeX RDF
30	Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu	Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	robust hardware, back-end design automation, power-constant architectures, DFY, side-channel attacks, DFM, mitigation
30	Sani R. Nassif, Vijay Pitchumani, Norma Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic	Variation-aware analysis: savior of the nanometer era?	DAC	2006	DBLP DOI BibTeX RDF	DFY, variability, yield
22	Giuseppe Nicosia, Giovanni Stracquadanio	A Design-for-Yield Algorithm to Assess and Improve the Structural and Energetic Robustness of Proteins and Drugs.	SEA	2009	DBLP DOI BibTeX RDF
22	David Cross, Eric Nequist, Louis Scheffer	A DFM aware, space based router.	ISPD	2007	DBLP DOI BibTeX RDF
22	Nagesh Nagapalli	DFT and Test: Ensuring Product Quality.	ISQED	2007	DBLP DOI BibTeX RDF
22	Resve A. Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki	DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering?	ISQED	2007	DBLP DOI BibTeX RDF
22	Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang	Design-for-testability and fault-tolerant techniques for FFT processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
22	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
22	Sanjiv Taneja	DFT Aware Layout - Layout Aware DFT.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
22	Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu	Failure Factor Based Yield Enhancement for SRAM Designs.	DFT	2004	DBLP DOI BibTeX RDF