Search results for "DNL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
117	Marko Kosunen, Jouko Vankka, Ilari Teikari, Kari Halonen	DNL and INL yield models for a current-steering D/A converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
63	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
59	Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongming Li 0004, Zhihua Wang 0001	A Pipelined A/D Conversion Technique with Low INL and DNL.	ISCAS	2007	DBLP DOI BibTeX RDF
59	Michael Wieckowski, John C. Liobe, Quentin Diduck, Martin Margala	A New Test Methodology For DNL Error In Flash ADC's.	DFT	2005	DBLP DOI BibTeX RDF
34	Alok Barua, Md. Tausiff	A Code Width Built-In-Self Test Circuit for 8-bit Pipelined ADC.	ICSEng	2011	DBLP DOI BibTeX RDF	Code width, DNL, INL, Missing code fault, BIST, fault coverage
29	Giulia Acconcia, Francesco Malanga, Serena Farina, Massimo Ghioni, Ivan Rech	A 1.9 ps-rms Precision Time-to-Amplitude Converter With 782 fs LSB and 0.79%-rms DNL.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
29	Junyong Lee, Gaim Jung, Seunghyun Kim, Minjae Lee	An 8-bit 1.24 mW Sub-1ps DNL Sub-1V Supply Inverter-Based Phase Interpolator Using a PVT-Tracking Adaptive-Bias Circuit.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
29	Jiajia Ni, Jianhuang Wu, Ahmed Elazab, Jing Tong, Zhengming Chen	DNL-Net: deformed non-local neural network for blood vessel segmentation.	BMC Medical Imaging	2022	DBLP DOI BibTeX RDF
29	Masayoshi Todorokihara	A 9 ps DNL/INL/RMS FPGA-Based Sigma Accumulation TDC with Unlimited Dynamic Range for Time-Based Analog Front End Applications.	IEEE SENSORS	2021	DBLP DOI BibTeX RDF
29	Panpan Zhang, Wenjiang Feng, Peng Zhao, Xiaoping Chen, Zongjiang Zhang	A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR.	IEEE Access	2019	DBLP DOI BibTeX RDF
29	Sohail Asghar, Sohaib Saadat Afridi, Anu Pillai, Anita Schuler, José M. de la Rosa 0001, Ivan John O'Connell	A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
29	Hua Fan 0001, Chen Wang, Hailiang Xiong, Quanyuan Feng, Dagang Li, Kelin Zhang, Xiaopeng Diao, Lishuang Lin, Hadi Heidari	A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).	NGCAS	2018	DBLP DOI BibTeX RDF
29	Sohail Asghar, Sohaib Saadat Afridi, Anu Pillai, Anita Schuler, José M. de la Rosa 0001, Ivan John O'Connell	A 2MS/s, 11.22 ENOB, 3.2 Vpp-d SAR ADC with improved DNL and offset calculation.	ISCAS	2018	DBLP DOI BibTeX RDF
29	Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang	Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs.	IEEE Trans. Instrum. Meas.	2016	DBLP DOI BibTeX RDF
29	Chi-Tung Ko, Kong-Pang Pun, Andreas Gothenberg	A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
29	Henry Park, Chih-Kong Ken Yang	Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
29	Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio	A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
29	Seyed Yahya Mortazavi, Abdolreza Nabavi	A New folding & interpolating ADC structure with reduced DNL/INL.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
29	Bettina Bauer-Messmer, Lukas Wotruba, Kalin Müller, Sandro Bischof, Rolf Grütter, Thomas Scharrenbach, Rolf Meile, Martin Hägeli, Jürg Schenker	The Data Centre Nature and Landscape (DNL): Service Oriented Architecture, Metadata Standards and Semantic Technologies in an Environmental Information System.	EnviroInfo (1)	2009	DBLP BibTeX RDF
29	Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	INL and DNL estimation based on noise for ADC test.	IEEE Trans. Instrum. Meas.	2004	DBLP DOI BibTeX RDF
29	Sunil Rafeeque, Vinita Vasudevan	An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC.	ISCAS (1)	2004	DBLP BibTeX RDF
29	Roland Holcer, Linus Michaeli, Ján Saliga	DNL ADC testing by the exponential shaped voltage.	IEEE Trans. Instrum. Meas.	2003	DBLP DOI BibTeX RDF
29	Yonghua Cong, Randall L. Geiger	Formulation of INL and DNL yield estimation in current-steering D/A converters.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
29	Ion E. Opris, Bill C. Wong, Sing W. Chin	A pipeline A/D converter architecture with low DNL.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
29	Sasikumar Cherubal, Abhijit Chatterjee	Optimal INL/DNL testing of A/D converters using a linear model.	ITC	2000	DBLP DOI BibTeX RDF
29	John Wu, Bosco Leung, Sehat Sutarja	A Mismatch Independent DNL Pipelined Analog to Digital Converter.	ISCAS	1994	DBLP DOI BibTeX RDF
29	Anchada Charoenrook, Mani Soma	Fault Diagnosis of Flash ADC using DNL Test.	ITC	1993	DBLP DOI BibTeX RDF
29	Shalabh Goyal, Abhijit Chatterjee	Linearity Testing of A/D Converters Using Selective Code Measurement.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Testing, Non-linearity, Manufacturing test, Analog-digital conversion
29	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
29	M. Khalilzadeh Agdam, Abdolreza Nabavi	A Low-Power High-Speed 4-Bit ADC for DS-UWB Communications.	ISVLSI	2007	DBLP DOI BibTeX RDF
29	Yongsheng Wang, Jinxiang Wang 0001, Fengchang Lai, Yizheng Ye	Optimal Schemes for ADC BIST Based on Histogram.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
29	João Goes, Nuno Paulino 0002, Guiomar Evans	On-chip built-in self-test of video-rate ADCs using Gaussian noise.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
29	Sunil Rafeeque, Vinita Vasudevan	A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	digital to analog converters, nonlinearity test, analog testing, mixed-signal BIST
29	Zhongjun Yu, Degang Chen 0001, Randall L. Geiger	1-D and 2-D switching strategies achieving near optimal INL for thermometer-coded current steering DACs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
29	Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang	An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
29	Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang	An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
29	Yuan-Tzu Ting, Li Wei Chao, Wei Chung Chao	A Practical Implementation Of Dynamic Testing Of An Ad Converter.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	AD converter, effective bits, differential nonlinearity, integral nonlinearity, mixed frequency estimation algorithm, weighted least square method, spectral average method, frequency domain estimation, logical analyzer, instrument controller, high speed data acquisition device, GPIB, Datel ADC-HS12B, programmable signal generator, algorithm, software, automatic testing, histogram, PC, signal to noise ratio, analogue-digital conversion, dynamic testing
15	Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A low power, variable resolution two-step flash ADC.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	two-step flash ADC, variable resolution, low power
15	Frank Sill, Davies W. de Lima Monteiro	Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor.	SBCCI	2009	DBLP DOI BibTeX RDF	pipelined SAC, error correction, ADC
15	Hee-Cheol Choi, Young-Ju Kim, Se-Won Lee, Jae-Yeol Han, Oh-Bong Kwon, Younglok Kim, Seung-Hoon Lee	A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Frank Ohnhaeuser, Mario Huemer	Methods to eliminate dynamic errors in high-performance SAR A/D converter.	ISCAS	2008	DBLP DOI BibTeX RDF
15	He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Santanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee	An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Chanyang Joo, Soojae Kim, Kwangsub Yoon	A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	binary decoder, pseudo-segmentation, swing reduced driver, low power, DAC
15	Shangquan Liang, Minglun Gao, Yong-Sheng Yin, Honghui Deng	A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications.	DELTA	2008	DBLP DOI BibTeX RDF	segmented current-steering, pseudorandom switching sequence, current switch driving circuit, unit current-cell
15	Erdem Serkan Erdogan, Sule Ozev	An ADC-BiST scheme using sequential code analysis.	DATE	2007	DBLP DOI BibTeX RDF
15	Hugo Daniel Hernández, Wilhelmus A. M. Van Noije, Elkim Roa, João Navarro Jr.	A small area 8bits 50MHz CMOS DAC for bluetooth transmitter.	SBCCI	2007	DBLP DOI BibTeX RDF	current-steering segmented, low area, bluetooth
15	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee	A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio	A 12-bit Current-Steering DAC with Calibration by Combination Selection.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire	On-Line Histogram Equalization for Flash ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai	A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli	A Power Optimized Base-Band Circuitry for the Low-IF Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Wen-Shen Chou, Shu-Chieh Yang, Fu-Lung Hsueh, Heng-Chang Huang, Chih-Ji Hsiao	A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Bi Yuan, Yi Zhang, Lili He 0001	A 8b 10Ms/s Low Power Pipelined A/D Converter.	ISQED	2007	DBLP DOI BibTeX RDF
15	Tae-Hwan Oh, Sang-Min Yoo, Kyoung-Ho Moon, Jae-Whui Kim	A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm2.	ISCAS	2006	DBLP DOI BibTeX RDF
15	P. Eloranta	A 14-bit D/A-converter with digital calibration.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A nanowatt ADC for ultra low power applications.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Sang-Min Yoo, Tae-Hwan Oh, Ho-Young Lee, Kyung-Ho Moon, Jae-Whui Kim	A 3.0V 12b 120 Msample/s CMOS pipelined ADC.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Biye Wang, Lili He 0001, Morris Jones	A low input, low-power dissipation CMOS ADC.	ISQED	2006	DBLP DOI BibTeX RDF
15	Gaurav Raja, Basabi Bhaumik	16-Bit Segmented Type Current Steering DAC for Video Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF	Digital-to-Analog Conversion, Segmentation, Matching
15	Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya	A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS.	VLSI Design	2006	DBLP DOI BibTeX RDF
15	Kyung-Hoon Lee, Young-Jae Cho, Hee-Cheol Choi, Yong-Hyun Park, Doo-Hwan Sa, Young-Lok Kim, Seung-Hoon Lee	A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Jae-Jin Jung, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim	A 6-bit 2.704Gsps DAC for DS-CDMA UWB.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Ka-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins	A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Seong-Min Ha, Tae-Kyu Nam, Kwang S. Yoon	An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento	Low Cost BIST for Static and Dynamic Testing of ADCs.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	ADC BIST, noise based testing, mixed-signal test
15	Nicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D'Amico, Andrea Baschirotto	A low-distortion 1.2 V DAC+filter for transmitters in wireless applications.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	Se-Won Kim, Young-Jae Cho, Kyung-Hoon Lee, Seung-Hoon Lee, Jae-Yup Lee, Hyun-Chul Noh, Hee-Sub Lee	An 8b 240 MS/s 1.36 mm2 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
15	Qiong Wu 0013, Albert Z. Wang	A 12 bits/200 MHz resolution/sampling/power-optimized ADC in 0.25µm SiGe BiCMOS.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng	A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	A. Seedher, Preetam Tadeparthy, K. A. S. Satheesh, V. T. Anuroop	Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen	A new CCII-based pipelined analog to digital converter.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Erhan Ozalevli, Christopher M. Twigg, Paul E. Hasler	10-bit programmable voltage-output digital-analog converter.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Ehab Shoukry, Madeleine Mony, David V. Plant	Design of a fully integrated array of high-voltage digital-to-analog converters.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov	A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
15	Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins	A frequency up-conversion and two-step channel selection embedded CMOS D/A interface.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	Yun-Che Wen	A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses.	VTS	2005	DBLP DOI BibTeX RDF
15	Chun-Yueh Huang, Tsung-Tien Hou, Chi-Chieh Chuang, Hung-Yu Wang	Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications.	IWSOC	2005	DBLP DOI BibTeX RDF
15	Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu	A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach.	ISLPED	2004	DBLP DOI BibTeX RDF	CMOS analog circuit, flash analog-to-digital converter, rail-to-rail, low power, comparator
15	Tae-Hwan Oh, Ho-Young Lee, Ho-Jin Park, Jae-Whui Kim	A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Kumar L. Parthasarathy, Turker Kuyel, Dana Price, Le Jin, Degang Chen 0001, Randall L. Geiger	BIST and production testing of ADCs using imprecise stimulus.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	ADC linearity, imprecision measurement, imprecision stimulus, built-in self-test, Analog and mixed-signal testing, production test
15	Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang	An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters.	ISVLSI	2003	DBLP DOI BibTeX RDF
15	Hyuen-Hee Bae, Jin-Sik Yoon, Myung-Jin Lee, Eun-Seok Shin, Seung-Hoon Lee	A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.	A self-testing method for the pipelined A/D converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao	A high-resolution and fast-conversion time-to-digital converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang	1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Andrea Gerosa, Andrea Neviani	A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Huseyin Dine, Franco Maloberti	An 8-bit current mode ripple folding A/D converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Susan Luschas, Hae-Seung Lee	Output impedance requirements for DACs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Farhang Vessal, C. André T. Salama	An 8-bit 2-GSample/s analog-to-digital converter in 0.5µm SiGe technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Jianjun Guo, Waisiu Law, Charles T. Peach, Ward J. Helms, David J. Allstot	A mixed-signal calibration technique for low-voltage CMOS 1.5-bit/stage pipeline data converters.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Seyed Mojtaba Atarodi	A 1.8-v high-speed 13-bit pipelined analog to digital converter for digital IF applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Sunil Rafeeque	Area efficient current steering DAC using current tuning.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
15	Yongsang Yoo, Minkyu Song	Design of a 1.8V 10bit 300MSPS CMOS digital-to-analog converter with a novel deglitching circuit and inverse thermometer decoder.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
15	Atit Tamtrakarn, N. Wongkomet	A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
15	Sotoudeh Hamedi-Hagh, C. André T. Salama	A 10 bit, 50 M sample/s, low power pipelined A/D converter for cable modem applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
15	Paolo Crippa, Massimo Conti, Claudio Turchetti	A statistical methodology for the design of high-performance current steering DAC's.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
15	Samgsuk Kim, Minkyu Song	An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver.	ISCAS (1)	2001	DBLP DOI BibTeX RDF