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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 37 occurrences of 32 keywords
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Results
Found 20 publication records. Showing 20 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
48 | Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro |
Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(4), pp. 275-292, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
error tolerant system, single event upset (SEU), Digital SignalProcessing (DSP), fault-tolerance, sigma-delta |
46 | Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García 0001 |
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 384-393, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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46 | Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor |
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 115-128, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer |
46 | B. Bosi, Guy Bois, Yvon Savaria |
Reconfigurable pipelined 2-D convolvers for fast digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(3), pp. 299-308, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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39 | Chuck Monahan, Forrest Brewer |
Symbolic execution of data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 80-85, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
combinational switching, data-path model, path constraints, bus hazards, register constraints, control encoding limitations, path-constrained model, DSP microprocessor, switching logic, connection constraints, operand constraints, scheduling, Boolean functions, Boolean functions, logic design, combinational circuits, data flow analysis, processor scheduling, symbolic execution, data flow graphs, digital signal processing chips, constraint handling, combinational logic, dataflow graphs, hazards and race conditions, memory elements |
26 | Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin |
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(2), pp. 155-168, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test |
25 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr. |
Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 224-229, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Speech-Recognition Systems (SRS), Recovery Blocks Scheme, Digital Signal Processing (DSP), On-Line Testing, Performance Degradation, Noise Immunity |
23 | Bor-Chin Chang 0001, Chunlong Hu, Mark Ilg |
Design and DSP microprocessor implementation of digital sinusoidal tracking controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACC ![In: American Control Conference, ACC 2005, Portland, OR, USA, 8-10 June, 2005, pp. 4947-4952, 2005, IEEE, 0-7803-9098-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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23 | Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat |
Division by Constant for the ST100 DSP Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 124-130, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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23 | Michael Dolle, Satwinder Jhand, Walter Lehner, Otto Müller, Manfred Schlett |
A 32-b RISC/DSP microprocessor with reduced complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(7), pp. 1056-1066, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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23 | Michael Dolle, Manfred Schlett |
A cost-effective RISC/DSP microprocessor for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 15(5), pp. 32-40, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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23 | Letizia Lo Presti, Giuseppe Cardamone |
A direct digital frequency synthesizer using an IIR filter implemented with a DSP microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (3) ![In: Proceedings of ICASSP '94: IEEE International Conference on Acoustics, Speech and Signal Processing, Adelaide, South Australia, Australia, April 19-22, 1994, pp. 201-204, 1994, IEEE Computer Society, 0-7803-1775-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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23 | Subramaniam Ganesan |
A dual-DSP microprocessor system for real-time digital correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 15(7), pp. 379-384, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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23 | Paruvachi V. R. Raja, Subramaniam Ganesan |
An SIMD multiple DSP microprocessor system for image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 15(9), pp. 493-501, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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23 | Michael Takefman, Paul Chow |
A streamlined DSP microprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1991 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '91, Toronto, Ontario, Canada, May 14-17, 1991, pp. 1257-1260, 1991, IEEE Computer Society, 0-7803-0003-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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23 | John P. Roesgen |
The ADSP-2100 DSP Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 6(6), pp. 49-59, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
23 | R. Hangartner, Vijay K. Jain |
32kbs ADPCM/PCM transcoder using TI-320 DSP microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '85, Tampa, Florida, USA, March 26-29, 1985, pp. 1421-1424, 1985, IEEE. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
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19 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr. |
A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(1), pp. 61-72, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
speech-recognition systems (SRS), digital signal processing (DSP), on-line testing, performance degradation, noise immunity, area overhead, recovery blocks |
13 | Javier Vega-Pineda, Mario Ignacio Chacon Murguia, Roberto Camarillo-Cisneros |
Synthesis of Pulsed-Coupled Neural Networks in FPGAs for Real-Time Image Segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2006, part of the IEEE World Congress on Computational Intelligence, WCCI 2006, Vancouver, BC, Canada, 16-21 July 2006, pp. 4051-4055, 2006, IEEE, 0-7803-9490-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede |
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 303-311, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
security, java, design, embedded systems, cryptography |
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