Search results for "DSP/microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
48	Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro	Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	error tolerant system, single event upset (SEU), Digital SignalProcessing (DSP), fault-tolerance, sigma-delta
46	Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García 0001	Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.	FPL	2004	DBLP DOI BibTeX RDF
46	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
46	B. Bosi, Guy Bois, Yvon Savaria	Reconfigurable pipelined 2-D convolvers for fast digital signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
39	Chuck Monahan, Forrest Brewer	Symbolic execution of data paths.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	combinational switching, data-path model, path constraints, bus hazards, register constraints, control encoding limitations, path-constrained model, DSP microprocessor, switching logic, connection constraints, operand constraints, scheduling, Boolean functions, Boolean functions, logic design, combinational circuits, data flow analysis, processor scheduling, symbolic execution, data flow graphs, digital signal processing chips, constraint handling, combinational logic, dataflow graphs, hazards and race conditions, memory elements
26	Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
25	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Speech-Recognition Systems (SRS), Recovery Blocks Scheme, Digital Signal Processing (DSP), On-Line Testing, Performance Degradation, Noise Immunity
23	Bor-Chin Chang 0001, Chunlong Hu, Mark Ilg	Design and DSP microprocessor implementation of digital sinusoidal tracking controllers.	ACC	2005	DBLP DOI BibTeX RDF
23	Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat	Division by Constant for the ST100 DSP Microprocessor.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
23	Michael Dolle, Satwinder Jhand, Walter Lehner, Otto Müller, Manfred Schlett	A 32-b RISC/DSP microprocessor with reduced complexity.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
23	Michael Dolle, Manfred Schlett	A cost-effective RISC/DSP microprocessor for embedded systems.	IEEE Micro	1995	DBLP DOI BibTeX RDF
23	Letizia Lo Presti, Giuseppe Cardamone	A direct digital frequency synthesizer using an IIR filter implemented with a DSP microprocessor.	ICASSP (3)	1994	DBLP DOI BibTeX RDF
23	Subramaniam Ganesan	A dual-DSP microprocessor system for real-time digital correlation.	Microprocess. Microsystems	1991	DBLP DOI BibTeX RDF
23	Paruvachi V. R. Raja, Subramaniam Ganesan	An SIMD multiple DSP microprocessor system for image processing.	Microprocess. Microsystems	1991	DBLP DOI BibTeX RDF
23	Michael Takefman, Paul Chow	A streamlined DSP microprocessor architecture.	ICASSP	1991	DBLP DOI BibTeX RDF
23	John P. Roesgen	The ADSP-2100 DSP Microprocessor.	IEEE Micro	1986	DBLP DOI BibTeX RDF
23	R. Hangartner, Vijay K. Jain	32kbs ADPCM/PCM transcoder using TI-320 DSP microprocessor.	ICASSP	1985	DBLP DOI BibTeX RDF
19	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	speech-recognition systems (SRS), digital signal processing (DSP), on-line testing, performance degradation, noise immunity, area overhead, recovery blocks
13	Javier Vega-Pineda, Mario Ignacio Chacon Murguia, Roberto Camarillo-Cisneros	Synthesis of Pulsed-Coupled Neural Networks in FPGAs for Real-Time Image Segmentation.	IJCNN	2006	DBLP DOI BibTeX RDF
13	Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede	Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques.	CASES	2004	DBLP DOI BibTeX RDF	security, java, design, embedded systems, cryptography