Search results for "Defects/faults"

Found 7 publication records. Showing 7 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
69	Abderrahim Doumar, Hideo Ito	Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources.	DFT	2000	DBLP DOI BibTeX RDF
39	Per Runeson, Anneliese Amschler Andrews	Detection or Isolation of Defects? An Experimental Comparison of Unit Testing and Code Inspection.	ISSRE	2003	DBLP DOI BibTeX RDF	Defect isolation, Empirical Study, Unit testing, Controlled Experiment, Defect detection, Code Inspection
24	Nachiappan Nagappan, E. Michael Maximilien, Thirumalesh Bhat, Laurie A. Williams	Realizing quality improvement through test driven development: results and experiences of four industrial teams.	Empir. Softw. Eng.	2008	DBLP DOI BibTeX RDF	Defects/faults, Empirical study, Test driven development, Development time
24	Gurindar S. Sohi	Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	cache memory organization, high performance VLSI processors, tolerance of defects faults, linear RAMs, trace-driven simulation analysis, storage management chips, VLSI, yield, fault location, buffer storage, performance degradation, random-access storage, integrated memory circuits
21	Norman E. Fenton, Martin Neil	A Critique of Software Defect Prediction Models.	IEEE Trans. Software Eng.	1999	DBLP DOI BibTeX RDF	Software faults and failures, fault-density, defects, Bayesian Belief Networks, complexity metrics
14	Claude Thibeault	On the Comparison of IDDQ and IDDQ Testing.	VTS	1999	DBLP DOI BibTeX RDF
14	Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen	An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching network fault diagnosis, reconfigurable VLSI/WSI array processors, switching network defects, killing error, testing circuit overhead, diagnosis time, mesh array, VLSI, parallel architectures, fault diagnosis, reconfigurable architectures, multiple faults, switching networks, wafer-scale integration, testing quality

Displaying result #1 - #7 of 7 (100 per page; Change: )