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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 26 occurrences of 24 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
69 | Abderrahim Doumar, Hideo Ito |
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 134-142, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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39 | Per Runeson, Anneliese Amschler Andrews |
Detection or Isolation of Defects? An Experimental Comparison of Unit Testing and Code Inspection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 14th International Symposium on Software Reliability Engineering (ISSRE 2003), 17-20 November 2003, Denver, CO, USA, pp. 3-13, 2003, IEEE Computer Society, 0-7695-2007-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Defect isolation, Empirical Study, Unit testing, Controlled Experiment, Defect detection, Code Inspection |
24 | Nachiappan Nagappan, E. Michael Maximilien, Thirumalesh Bhat, Laurie A. Williams |
Realizing quality improvement through test driven development: results and experiences of four industrial teams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Empir. Softw. Eng. ![In: Empir. Softw. Eng. 13(3), pp. 289-302, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Defects/faults, Empirical study, Test driven development, Development time |
24 | Gurindar S. Sohi |
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(4), pp. 484-492, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
cache memory organization, high performance VLSI processors, tolerance of defects faults, linear RAMs, trace-driven simulation analysis, storage management chips, VLSI, yield, fault location, buffer storage, performance degradation, random-access storage, integrated memory circuits |
21 | Norman E. Fenton, Martin Neil |
A Critique of Software Defect Prediction Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 25(5), pp. 675-689, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Software faults and failures, fault-density, defects, Bayesian Belief Networks, complexity metrics |
14 | Claude Thibeault |
On the Comparison of IDDQ and IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 143-151, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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14 | Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen |
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 349-354, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
switching network fault diagnosis, reconfigurable VLSI/WSI array processors, switching network defects, killing error, testing circuit overhead, diagnosis time, mesh array, VLSI, parallel architectures, fault diagnosis, reconfigurable architectures, multiple faults, switching networks, wafer-scale integration, testing quality |
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