Results
Found 17 publication records. Showing 17 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
24 | S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates |
16 | Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebel |
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Power-Simulation, Power-Estimation, Power-Modelling, Delay-Modelling, Timing-Modelling |
15 | Constantin Florin Caruntu, Corneliu Lazar |
Network delay predictive compensation based on time-delay modelling as disturbance. |
Int. J. Control |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Uwe Hinsberger, Reiner Kolla |
Cell based performance optimization of combinational circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
10 | Birgit Vogel-Heuser, Yash Deshpande, Fandi Bi, Jingyun Zhao, Dominik Hujo, Wolfgang Kellerer, André Kraft, Bernd Vojanec, Timo Markert |
Delay Modelling and Measurement of Multi-Agent Systems with Digital Twins in a Gear Assembly Use Case. |
CASE |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Aya Aboudina, Alaa Itani, Ehab Diab, Siva Srikukenthiran, Amer Shalaby |
Evaluation of bus bridging scenarios for railway service disruption management: a users' delay modelling tool. |
Public Transp. |
2021 |
DBLP DOI BibTeX RDF |
|
10 | Sohaib Majzoub, Mottaqiallah Taouil, Said Hamdioui |
System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation. |
J. Low Power Electron. |
2019 |
DBLP DOI BibTeX RDF |
|
10 | Chenxi Ni, Gordon Russell 0002, Alex Bystrov |
Statistical delay modelling of manufacturing process variations at system level. |
NEWCAS |
2012 |
DBLP DOI BibTeX RDF |
|
10 | Albert Sunny, Joy Kuri, Saurabh Aggarwal |
Delay Modelling for a Single-hop Wireless Mesh Network under Light Aggregate Traffic |
CoRR |
2010 |
DBLP BibTeX RDF |
|
10 | Albert Sunny, Joy Kuri, Saurabh Aggarwal |
Delay Modelling for Single Cell IEEE 802.11 WLANs Using a Random Polling System |
CoRR |
2010 |
DBLP BibTeX RDF |
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10 | Albert Sunny, Joy Kuri, Saurabh Aggarwal |
Application Delay Modelling for Variable Length Packets in Single Cell IEEE 802.11 WLANs |
CoRR |
2010 |
DBLP BibTeX RDF |
|
10 | Hilmi Berk Celikoglu, Mauro Dell'Orco |
Delay Modelling at Unsignalized Highway Nodes with Radial Basis Function Neural Networks. |
ISNN (1) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Manuel Barrio, Kevin Burrage, André Leier, Tianhai Tian |
Oscillatory Regulation of Hes1: Discrete Stochastic Delay Modelling and Simulation. |
PLoS Comput. Biol. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Ian A. Hiskens |
Time-delay modelling for multi-layer power systems. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Jean Michel Daga, Michel Robert, Daniel Auvergne |
Delay modelling improvement for low voltage applications. |
EURO-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
10 | Isabel M. G. Lourtie, G. Clifford Carter |
Signal detection in the presence of inaccurate multipath time delay modelling. |
ICASSP |
1990 |
DBLP DOI BibTeX RDF |
|
10 | Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury |
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
spice verification, primary-path, secondary-path, timing analysis, assertion, assertibility |
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