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Found 17 publication records. Showing 17 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
24 | S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 361-366, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates |
16 | Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebel |
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 356-361, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Power-Simulation, Power-Estimation, Power-Modelling, Delay-Modelling, Timing-Modelling |
15 | Constantin Florin Caruntu, Corneliu Lazar |
Network delay predictive compensation based on time-delay modelling as disturbance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Control ![In: Int. J. Control 87(10), pp. 2012-2026, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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12 | Uwe Hinsberger, Reiner Kolla |
Cell based performance optimization of combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 594-599, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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10 | Birgit Vogel-Heuser, Yash Deshpande, Fandi Bi, Jingyun Zhao, Dominik Hujo, Wolfgang Kellerer, André Kraft, Bernd Vojanec, Timo Markert |
Delay Modelling and Measurement of Multi-Agent Systems with Digital Twins in a Gear Assembly Use Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASE ![In: 19th IEEE International Conference on Automation Science and Engineering, CASE 2023, Auckland, New Zealand, August 26-30, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-2069-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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10 | Aya Aboudina, Alaa Itani, Ehab Diab, Siva Srikukenthiran, Amer Shalaby |
Evaluation of bus bridging scenarios for railway service disruption management: a users' delay modelling tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Public Transp. ![In: Public Transp. 13(3), pp. 457-481, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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10 | Sohaib Majzoub, Mottaqiallah Taouil, Said Hamdioui |
System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 15(1), pp. 1-10, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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10 | Chenxi Ni, Gordon Russell 0002, Alex Bystrov |
Statistical delay modelling of manufacturing process variations at system level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 10th IEEE International NEWCAS Conference, Montreal, QC, Canada, June 17-20, 2012, pp. 133-136, 2012, IEEE, 978-1-4673-0857-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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10 | Albert Sunny, Joy Kuri, Saurabh Aggarwal |
Delay Modelling for a Single-hop Wireless Mesh Network under Light Aggregate Traffic ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1009.0448, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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10 | Albert Sunny, Joy Kuri, Saurabh Aggarwal |
Delay Modelling for Single Cell IEEE 802.11 WLANs Using a Random Polling System ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1009.3468, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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10 | Albert Sunny, Joy Kuri, Saurabh Aggarwal |
Application Delay Modelling for Variable Length Packets in Single Cell IEEE 802.11 WLANs ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1009.5321, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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10 | Hilmi Berk Celikoglu, Mauro Dell'Orco |
Delay Modelling at Unsignalized Highway Nodes with Radial Basis Function Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2007, 4th International Symposium on Neural Networks, ISNN 2007, Nanjing, China, June 3-7, 2007, Proceedings, Part I, pp. 562-571, 2007, Springer, 978-3-540-72382-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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10 | Manuel Barrio, Kevin Burrage, André Leier, Tianhai Tian |
Oscillatory Regulation of Hes1: Discrete Stochastic Delay Modelling and Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLoS Comput. Biol. ![In: PLoS Comput. Biol. 2(9), 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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10 | Ian A. Hiskens |
Time-delay modelling for multi-layer power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 316-319, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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10 | Jean Michel Daga, Michel Robert, Daniel Auvergne |
Delay modelling improvement for low voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 216-221, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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10 | Isabel M. G. Lourtie, G. Clifford Carter |
Signal detection in the presence of inaccurate multipath time delay modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1990 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '90, Albuquerque, New Mexico, USA, April 3-6, 1990, pp. 2751-2754, 1990, IEEE. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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10 | Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury |
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 175-180, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
spice verification, primary-path, secondary-path, timing analysis, assertion, assertibility |
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