Search results for "Divider"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
113	Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt	High speed digital CMOS divide-by-N fequency divider.	ISCAS	2008	DBLP DOI BibTeX RDF
101	Anders Berkeman, Viktor Öwall	A configurable divider using digit recurrence.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
89	Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije	A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.	SBCCI	2005	DBLP DOI BibTeX RDF	high speed digital circuit, low power, prescaler, frequency synthesizer
76	C.-C. Wang, C. J. Huang, G.-C. Lin	A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
76	Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi	A C-testable carry-free divider.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
74	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
74	Chris van den Bos, Chris J. M. Verhoeven	Frequency division using an injection-locked relaxation oscillator.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
64	Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su	A Sub-1V Low-Power High-Speed Static Frequency Divider.	ISCAS	2007	DBLP DOI BibTeX RDF
64	Muhammad Usama, Tad A. Kwasniewski	A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
64	Sandeep B. Singh, Jayanta Biswas, S. K. Nandy 0001	A Cost Effective Pipelined Divider for Double Precision Floating Point Number.	ASAP	2006	DBLP DOI BibTeX RDF
64	Woo-Chan Park, Tack-Don Han, Sung-Bong Yang	A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
64	Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Yoshitaka Matsuda, Yutaka Fukui	PLL frequency synthesizer with an auxiliary programmable divider.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
63	Stephan Henzler, Siegmar Koeppe	High-speed low-power frequency divider with intrinsic phase rotator.	ISLPED	2006	DBLP DOI BibTeX RDF	phase-rotator, pre-scaler, low-power, divider
61	Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Hidekazu Ishii, Yoshitaka Matsuda, Yutaka Fukui	Dead-zone-less PLL frequency synthesizer by hybrid phase detectors.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
60	Chanyutt Arjhan, Raghvendra G. Deshmukh	A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
52	Alireza Saberkari, Shahriar B. Shokouhi, Azadeh Kiani, Fereshteh Poorahangaryan	A novel low power static frequency divider based on the GDI technique.	CCECE	2009	DBLP DOI BibTeX RDF
52	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking and Code-Disjoint Non-Restoring Array Divider.	IOLTS	2006	DBLP DOI BibTeX RDF
52	Xiaopeng Yu, Manh Anh Do, Lin Jia, Jianguo Ma, Kiat Seng Yeo	Design of a low power wide-band high resolution programmable frequency divider.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
52	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
52	Zhenhua Wang	A virtually jitter-free fractional-N divider for a Bluetooth radio.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
52	KiJong Lee, Kiyoung Choi	Self-timed divider based on RSD number system.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
51	Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner	A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology.	ISLPED	2003	DBLP DOI BibTeX RDF	RF circuit, SOI CMOS, frequency divider, low power, CML
51	Suchitav Khadanga	Synchronous programmable divider design for PLL Using 0.18 um cmos technology.	IWSOC	2003	DBLP DOI BibTeX RDF	programmable divider, CMOS integrated circuits, phase locked loop, PLL, Prescaler, frequency synthesizers
49	David L. Harris, Stuart F. Oberman, Mark Horowitz	SRT Division Architectures and Implementations.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	skew-tolerant, Computer arithmetic, floating point units, SRT division, domino circuits
48	Syed Mahfuzul Aziz, S. J. Carr	On C-Testability of Carry Free Dividers.	DELTA	2002	DBLP DOI BibTeX RDF	Carry-free, C-Testability, Divider, Radix-2
48	Jean-Paul Theis, Harald Schlimper	Ultrafast compact CMOS dividers.	ICPADS	1997	DBLP DOI BibTeX RDF	CMOS dividers, ultrafast, restoring division, floating-point division, 0.3 mum, parallelization, timing, layout, compact, dividing circuits, divider circuits
40	Melina Apostolidou, Peter G. M. Baltus, Cicero S. Vaucher	Phase noise in frequency divider circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
40	K. Scott Hemmert, Keith D. Underwood	Floating-Point Divider Design for FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
40	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A radix-10 SRT divider based on alternative BCD codings.	ICCD	2007	DBLP DOI BibTeX RDF
40	Liang Wang 0024, Suge Yue, Yuanfu Zhao, Long Fan	An SEU-Tolerant Programmable Frequency Divider.	ISQED	2007	DBLP DOI BibTeX RDF
40	Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski	A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider.	CCECE	2006	DBLP DOI BibTeX RDF
40	Xinyu Guo, Carl Sechen	High Speed Redundant Adder and Divider in Output Prediction Logic.	ISVLSI	2005	DBLP DOI BibTeX RDF
40	Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Taewhan Kim	An efficient inverse multiplier/divider architecture for cryptography systems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
40	Uroschanit Yodprasit, Christian C. Enz	Nonlinear analysis of a Colpitts injection-locked frequency divider.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
40	Khanittha Kaewdang, Chalermpan Fongsamut, Wanlop Surakampontorn	A wide-band current-mode OTA-based analog multiplier-divider.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
40	Spiridon Vlassis, Stilianos Siskos	Analog CMOS four-quadrant multiplier and divider.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
40	David Eisig, Josh Rotstain, Israel Koren	The design of a 64-bit integer multiplier/divider unit.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
39	Zhaofeng He, Junshuang Ma, Ming Yang	Design of Automatic Multiple Musical Performance Circuit System Based on Numerical Control Frequency Divider.	MVHI	2010	DBLP DOI BibTeX RDF	frequency divider, VHDL, musical performance
39	Hongli Tian, Shuo Shi, Jun Zhang, Hongdong Zhao	Controllable Arbitrary Integer Frequency Divider Based on VHDL.	JCAI	2009	DBLP DOI BibTeX RDF	50% duty cycle, frequency divider, FPGA, VHDL, CPLD
37	Stephan Henzler, Siegmar Koeppe	Design and Application of Power Optimized High-Speed CMOS Frequency Dividers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
37	Marcelo E. Kaihara, Naofumi Takagi	A Hardware Algorithm for Modular Multiplication/Division.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	modular division, cryptography, Computer arithmetic, modular multiplication, redundant representation, hardware algorithm
37	Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi 0001	High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables.	ISMVL	2000	DBLP DOI BibTeX RDF	Quotient digit selection tables, High-radix division, VLSI, Computer arithmetic, Signed-digit number systems, SRT division
37	Alberto Nannarelli, Tomás Lang	Power-delay tradeoffs for radix-4 and radix-8 dividers.	ISLPED	1998	DBLP DOI BibTeX RDF
37	W. Lynn Gallagher, Earl E. Swartzlander Jr.	Error-Correcting Goldschmidt Dividers Using Time Shared TMR.	DFT	1998	DBLP DOI BibTeX RDF	Goldschmidt's algorithm, time shared TMR, TSTMR fault tolerance, fault tolerant arithmetic, division
37	W. Lynn Gallagher, Earl E. Swartzlander Jr.	Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR.	DFT	1997	DBLP DOI BibTeX RDF
37	Chin-Long Wey	Built-in self-test (BIST) design of high-speed carry-free dividers.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
37	Randal E. Bryant	Multipliers and Dividers: Insights on Arithmetic Circuits Verification (Extended Abstract).	CAV	1995	DBLP DOI BibTeX RDF
37	Niraj K. Jha, Abha Ahuja	Easily testable nonrestoring and restoring gate-level cellular array dividers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
37	Hosahalli R. Srinivas, Keshab K. Parhi	High-speed VLSI arithmetic processor architectures using hybrid number representation.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
36	Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A Totally Self-Checking Dynamic Asynchronous Datapath.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider
36	Naofumi Takagi, Takashi Horiyama	A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	on-the-fly conversion, adder, Arithmetic circuit, divider
30	Sheng-Lyang Jang, Chia-Tung Hsieh, Tzu-Chin Yang, Miin-Horng Juang	Current Reused 8: 1 Injection Locked Frequency Divider Using Unbalanced Ring Oscillator Frequency Divider.	IEEE Access	2021	DBLP DOI BibTeX RDF
30	Atsushi Domae, Takehiko Oe, Syogo Kiryu, Nobu-hisa Kaneko	Experimental Demonstration of Current Dependence Evaluation of Voltage Divider Based on Quantized Hall Resistance Voltage Divider.	IEEE Trans. Instrum. Meas.	2017	DBLP DOI BibTeX RDF
30	Ayman S. Al-Zayed, Mohammed A. Kourah	The design of an integrated diplexer-power divider based on dual-band impedance transformers and a five-port power-divider.	AFRICON	2017	DBLP DOI BibTeX RDF
30	Young-Ho Choi, Jae-Yoon Sim, Hong-June Park	A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator.	ISOCC	2012	DBLP DOI BibTeX RDF
27	Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto	Multiplier-based double precision floating point divider according to the IEEE-754 standard.	ARC	2008	DBLP DOI BibTeX RDF
27	Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li	A novel VLSI iterative divider architecture for fast quotient generation.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Divider Using Newton-Raphson Iteration.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Newton-Raphson iteration, initial approximation, computer arithmetic, floating-point, division, hardware design, decimal
27	Jian-Hong Fang, Norman M. Filiol, Tom A. D. Riley, Miles A. Copeland	A Second Order Delta-Sigma Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo	A New Phase Noise Model for TSPC based divider.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
27	Maria J. Avedillo, José M. Quintana, José L. Huertas	Robust frequency divider based on resonant tunneling devices.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
27	Mika Nyström, Elaine Ou, Alain J. Martin	An Eight-Bit Divider Implemented in Asynchronous Pulse Logic.	ASYNC	2004	DBLP DOI BibTeX RDF
27	Amin Q. Safarian, Payam Heydari	Design and analysis of a distributed regenerative frequency divider using distributed mixer.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
27	Gang Li, Brent Maundy	A novel four quadrant CMOS analog multiplier/divider.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
27	Guenter Gerwig, Holger Wetter, Eric M. Schwarz, Juergen Haess	High Performance Floating-Point Unit with 116 Bit Wide Divider.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
27	Sanya Amnartpluk, Chuwong Phongcharoenpanich, Sompol Kosulvit, Monai Krairiksh	A power divider using linear electric probes coupling inside conducting cylindrical cavity.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
27	Günter Ritzberger, Josef Böck, Herbert Knapp, Ludwig Treitinger, Arpad L. Scholtz	38 GHz low-power static frequency divider in SiGe bipolar technology.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
27	Roope Kaivola, Mark D. Aagaard	Divider Circuit Verification with Model Checking and Theorem Proving.	TPHOLs	2000	DBLP DOI BibTeX RDF
27	Alberto Nannarelli, Tomás Lang	Low-Power Divider.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Floating-point division, low-power, digit-recurrence division
27	Antonio J. López-Martín, Alfonso Carlosena	Geometric-mean based current-mode CMOS multiplier/divider.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
27	Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet	Verifying a Self-Timed Divider.	ASYNC	1998	DBLP DOI BibTeX RDF	model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence
25	Marco Bucci, Raimondo Luzzi, Santos Torres Vargas	A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications.	DDECS	2008	DBLP DOI BibTeX RDF
25	Leendert van den Berg, Duncan G. Elliott	An alias-locked loop frequency synthesis architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
25	Behzad Razavi	CMOS Transceivers at 60 GHz and Beyond1.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Anuja Jayraj Thakkar, Abdel Ejnioui	Pipelining of double precision floating point division and square root operations.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, floating point, division, square root
25	David Kubánek, Kamil Vrba, Radek Sponar	Low-Pass Filter with UCC Suitable for Data Systems.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
25	Tung N. Pham, Earl E. Swartzlander Jr.	Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology.	ASAP	2006	DBLP DOI BibTeX RDF
25	Abdulrahman Al-Humaidan, Saleh R. Al-Araji, Mahmoud Al-Qutayri	Frequency Synthesizer for Wireless Applications using TDTL.	APCCAS	2006	DBLP DOI BibTeX RDF
25	Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi	A Hardware Algorithm for Integer Division.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
25	Kei-Yong Khoo, Alan N. Willson Jr.	Efficient VLSI implementation of N/N integer division.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
25	Lei Yang 0019, Cherry Wakayama, C.-J. Richard Shi	Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	jitter noise, PLL, phase noise, frequency synthesizer
25	Chang Hoon Kim, Soonhak Kwon, Jong Jin Kim, Chun Pyo Hong	A Compact and Fast Division Architecture for a Finite Field.	ICCSA (1)	2003	DBLP DOI BibTeX RDF	Extended Binary GCD, VLSI, Finite Field, Division
25	Zhan Yu	Low power finite field multiplication and division in re-configurable Reed-Solomon codec.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
25	Irene Finocchi, Rossella Petreschi	Hierarchical Clustering of Trees: Algorithms and Experiments.	ALENEX	2001	DBLP DOI BibTeX RDF
25	W. Lynn Gallagher, Earl E. Swartzlander Jr.	Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	fault-tolerant arithmetic, Newton-Raphson division, Goldschmidt division, time shared TMR, Division
25	G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos	Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
25	Alberto Nannarelli, Tomás Lang	Low-Power Radix-4 Combined Division and Square Root.	ICCD	1999	DBLP DOI BibTeX RDF
25	Gianluca Cornetta, Jordi Cortadella	A Radix-16 SRT Division Unit with Speculation of the Quotient Digits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
25	W. Lynn Gallagher, Earl E. Swartzlander Jr.	Power Consumption in Fast Dividers Using Time Shared TMR.	DFT	1999	DBLP DOI BibTeX RDF	Goldschmidt, time shared TMR, fault tolerant arithmetic, fault tolerance, division, TMR, Newton-Raphson
25	Yuan Yan Tang, Yu Tao 0015	Feature Extraction by Fractal Dimensions.	ICDAR	1999	DBLP DOI BibTeX RDF
24	Alaaeldin Amin, M. Waleed Shinwari	High-Radix Multiplier-Dividers: Theory, Design, and Hardware.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	quotient digit selection, multiplier-divider, Computer arithmetic, division, SRT
24	Guilu Long 0001, Yang Liu	Duality quantum computing.	Frontiers Comput. Sci. China	2008	DBLP DOI BibTeX RDF	duality computer, duality quantum computer, duality parallelism, duality gates, duality mode, generalized quantum gates, combiner, divider
24	Franco P. Preparata, Jean Vuillemin	Practical Cellular Dividers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	parallel division algorithms, nonrestoring online division methods, divider/multiplier, RSA cryptography, greatest common divisor computations, parallel algorithms, signal processing, digital arithmetic, modular arithmetic, redundant representations, floating-point units, dividing circuits, signed, systolic, digit-serial multiplier
15	Zhiyu Qian, Yongrong Shi, Juan Han, Shijie Liu, Yifan Guo, Longbao Cheng, Yongjiu Zhao, Tangsheng Chen	X-Band Power Divider Design and Its Network for Active Electronically Scanned Array Vertical Integration.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
15	Siran Zhang, Hongmei Liu 0007, Shuyi Chen, Zhongbao Wang, Shaojun Fang	Wideband Filtering Power Divider With Unequal Power Division Ratio and All-Frequency Input Absorptive Feature.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
15	Qiuyi Wu, Qi Cheng, Yimin Yang, Xiaowei Shi	Compact Waveguide Power Divider Using Magic-Tee With Integrated Impedance Transformers.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
15	Ashish Kumar, Meenakshi Rawat	A Modified Analog Predistorter Using Tunable Power Divider for Wideband 5G Transmitters.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
15	Xian-Long Yang, Xiao-Wei Zhu, Xiang Wang	An X-Band Low Phase Noise Parallel-Feedback Oscillator Based on SIW Dual-Mode Filtering Power Divider.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
15	Sajjad Akherati, Jiaxuan Cai, Xinmiao Zhang	Low-Complexity Integer Divider Architecture for Homomorphic Encryption.	CoRR	2024	DBLP DOI BibTeX RDF
15	Siyi Wang, Eugene Lim, Anupam Chattopadhyay	Boosting the Efficiency of Quantum Divider through Effective Design Space Exploration.	CoRR	2024	DBLP DOI BibTeX RDF