Search results for "EDA-tool"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
70	Robert N. Blair, Jacques Benkoski	How Do You Select A High Quality EDA Tool Flow?.	ISQED	2000	DBLP DOI BibTeX RDF
60	James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu	A new efficient EDA tool design methodology.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Net Framework, C?, ESys.Net, attribute programming, embedded systems, SoC, VHDL, SystemC, modeling and simulation, CoDesign
53	Christos P. Sotiriou	Implementing asynchronous circuits using a conventional EDA tool-flow.	DAC	2002	DBLP DOI BibTeX RDF	tool-flow, asynchronous, EDA
47	Giora Ben-Yaacov, Pramod Suratkar, Marsha Holliday, Karen Bartleson	Advancing Quality of EDA Software (invited).	ISQED	2002	DBLP DOI BibTeX RDF
47	Amir A. Khwaja	Enhancing extensibility of the design rule checker of an EDA tool by object-oriented modeling.	COMPSAC	1997	DBLP DOI BibTeX RDF	design rule checker, design rule checking systems, electronic design automation tools, semiconductor technology, DRC systems, DRC module, IC package design tool, object oriented modeling technique, abstraction, inheritance, extensibility, object oriented modeling, encapsulation, circuit CAD, dynamic binding, EDA tool
42	Lech Józwiak, Alexander Douglas	Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators.	ITNG	2008	DBLP DOI BibTeX RDF	re-configurable computing, heterogeneous pipelined accelerators, hardware synthesis, EDA-tool
33	Walid Ibrahim	A Novel EDA Tool for VLSI Test Vectors Management.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Test vectors selection, Genetic algorithms, Verification, VLSI, EDA tools
32	Richard Goldman, Karen Bartleson	Tool Interoperability is Key to Improved Design Quality.	ISQED	2000	DBLP DOI BibTeX RDF
31	Gary Smith 0001	A new era for CAD.	ISPD	2005	DBLP DOI BibTeX RDF
29	Michaela Guiney, Eric Leavitt	An introduction to OpenAccess: an open source data model and API for IC design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
29	Vijay Pitchumani	Embedded tutorial I: design for manufacturability.	ASP-DAC	2005	DBLP DOI BibTeX RDF
29	Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore	Analog intellectual property: now? Or never?	DAC	2002	DBLP DOI BibTeX RDF
25	Mark C. Johnson	igital Design Education Infrastructure Using Multiple EDA Tool Vendors and Multiple Modes of Tool Access.	MSE	2001	DBLP DOI BibTeX RDF
25	Pinhong Chen, Kurt Keutzer, Desmond Kirkpatrick	Scripting for EDA Tools: A Case Study.	ISQED	2001	DBLP DOI BibTeX RDF
23	Lionel Bening, Harry Foster	Optimizing Multiple EDA Tools within the ASIC Design Flow.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
22	Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi	Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	ODYSSEY, embedded systems, ASIP, JPEG
21	Pingakshya Goswami, Dinesh Bhatia	Application of Machine Learning in FPGA EDA Tool Development.	IEEE Access	2023	DBLP DOI BibTeX RDF
21	Khader Mohammad, Nirmeen Al-Sheikh	Efficient Implementation of a 4x4 Enhanced Pipeline Multiplier Using Electric EDA Tool.	ICM	2023	DBLP DOI BibTeX RDF
21	Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim	DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.	DATE	2023	DBLP DOI BibTeX RDF
21	Florian Klemme, Sami Salamin, Hussam Amrouch	Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows.	DATE	2023	DBLP DOI BibTeX RDF
21	Hwapyong Kim, Taewhan Kim	Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
21	Johannes Bastl, Zhihong Lei, Jonas Meier, Ralf Wunderlich, Stefan Heinen	A Design Flow and EDA-Tool for an Automated Implementation of ASIC Configuration Interfaces.	SMACD	2022	DBLP DOI BibTeX RDF
21	Pere Millán-Martínez, Ramon Oller	A Graphical EDA Tool with ggplot2: brinton.	R J.	2020	DBLP DOI BibTeX RDF
21	Jingsong Chen, Jian Kuang 0001, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young	PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning.	ICCAD	2020	DBLP DOI BibTeX RDF
21	Munish Jassi, Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann	Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
21	Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi	Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification.	IVSW	2018	DBLP DOI BibTeX RDF
21	Antti Kamppi, Esko Pekkarinen, Janne Virtanen, Joni-Matti Määttä, Juho Järvinen, Lauri Matilainen, Mikko Teuho, Timo D. Hämäläinen	Kactus2: A graphical EDA tool built on the IP-XACT standard.	J. Open Source Softw.	2017	DBLP DOI BibTeX RDF
21	Y. Q. de Aguiar, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Permanent and single event transient faults reliability evaluation EDA tool.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
21	Minas Dasygenis, Ioannis Petrousov	A networking EDA tool for multi-vector multiplication IP circuits.	DTIS	2015	DBLP DOI BibTeX RDF
21	Giannis Petrousov, Minas Dasygenis	A unique network EDA tool to create optimized ad hoc binary to residue number system converters.	PATMOS	2014	DBLP DOI BibTeX RDF
21	Minas Dasygenis	A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration.	DTIS	2014	DBLP DOI BibTeX RDF
21	Yogesh Dilip Save, Rajalekshmi Rakhi, N. D. Shambhulingayya, Ambikeshwar Srivastava, Manas Ranjan Das, Saket Choudhary, Kannan M. Moudgalya	Oscad: An open source EDA tool for circuit design, simulation, analysis and PCB design.	ICECS	2013	DBLP DOI BibTeX RDF
21	Walid Ibrahim, Valeriu Beiu, Azam Beg	GREDA: A Fast and More Accurate Gate Reliability EDA Tool.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
21	Behnam Ghavami, Hossein Pedram, Mehrdad Najibi	An EDA tool for implementation of low power and secure crypto-chips.	Comput. Electr. Eng.	2009	DBLP DOI BibTeX RDF
21	Walid Ibrahim, Valeriu Beiu	A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations.	NanoNet	2009	DBLP DOI BibTeX RDF	nano-circuits, Reliability, Bayesian networks, EDA tools
21	Charles C. Chiang, Subarna Sinha	The road to 3D EDA tool readiness.	ASP-DAC	2009	DBLP DOI BibTeX RDF
21	Benjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann	4.25 Gb/s laser driver: design challenges and EDA tool limitations.	DAC	2006	DBLP DOI BibTeX RDF	electrical to optical interface, laser diode, laser driver
21	Jayanta Mukherjee 0002, Jason Parry, WenHua Dai, Patrick Roblin, Steven B. Bibyk, Jongsoo Lee	RFIC Loadpull Simulations Implementing Best Practice RF and Mixed-Signal Design using an Integrated Agilent and Cadence EDA tool.	MSE	2003	DBLP DOI BibTeX RDF
21	Rick Miller	VHDL-based EDA Tool Implementation with Java.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Hardware/Software CoSynthesis, Java, VHDL
21	Luca Benini, Alessandro Bogliolo, Giovanni De Micheli	Distributed EDA Tool Integration: The PPP Paradigm.	ICCD	1996	DBLP DOI BibTeX RDF	sampling, processor simulation
20	Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian	A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	built-in self-test, embedded cores, EDA tools
12	Valeriy Sukharev, Ara Markosian, Armen Kteyan, Levon Manukyan, Nikolay Khachatryan, Jun-Ho Choy, Hasmik Lazaryan, Henrik Hovsepyan, Seiji Onoue, Takuo Kikuchi, Tetsuya Kamigaki	Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation.	ISQED	2009	DBLP DOI BibTeX RDF
12	Aleksander Slusarczyk, Lech Józwiak	Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis.	ISQED	2002	DBLP DOI BibTeX RDF
11	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
11	Matt Nowak, Jose Corleto, Christopher Chun, Riko Radojcic	Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration.	DAC	2008	DBLP DOI BibTeX RDF	design technology integration, design exploration, pathfinding
11	Shuming Chen, Xiangyuan Liu	A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs.	NOCS	2007	DBLP DOI BibTeX RDF	differential-signaling, insertion methodology, on-chip interconnects, low-swing
11	Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka	A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery.	DSN	2007	DBLP DOI BibTeX RDF
11	Vijay K. Madisetti	Electronic System, Platform, and Package Codesign.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	System-Level Design Automation, Electronic Packaging, System-on-Chip, Platform-Based Design, System-in-Package, System-on-Package
11	Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu	Automatic Generation of Programmable Parallel CRC & Scrambler Designs.	SiPS	2006	DBLP DOI BibTeX RDF
11	Masaya Yoshikawa, Hidekazu Terai	Performance driven placement technique based on collaboration of software and hardware.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
11	Masaya Yoshikawa, Hidekazu Terai	A Hierarchical Parallel Placement Technique based on Genetic Algorithm.	ISDA	2005	DBLP DOI BibTeX RDF
11	Yeshwant Kolla, Yong-Bin Kim, John Carter	A novel 32-bit scalable multiplier architecture.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	CMOS VLSI, architecture, multiplier
11	Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi	54x54-bit radix-4 multiplier based on modified booth algorithm.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	compressor, adder, multiplier, booth encoder, wallace tree
11	Ming-Hsiu Lai, Ming-Feng Yu, Sau-Gee Chen	An efficient modified Phong shading algorithm & its low-complexity realization.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
11	Adil Koukab, Catherine Dehollain, Michel J. Declercq	HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC.	DAC	2002	DBLP DOI BibTeX RDF	mixed-signal noise, supply noise, noise, numerical analysis, boundary-element-method, substrate noise, switching circuits, substrate coupling
11	Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun-Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee	Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern.	ASP-DAC	2001	DBLP DOI BibTeX RDF	Decision feedback equalizer, reusable VLSI implementation, FIR filter, QAM
11	Hilary J. Kahn, Andy Carpenter, Nigel A. Whitaker	A Web-Based System for Assessing and Searching for Designs.	DATE	2000	DBLP DOI BibTeX RDF
11	Chris W. H. Strolenberg	Stay Away from Minimum Design-Rule Values.	DATE	2000	DBLP DOI BibTeX RDF