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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 59 occurrences of 51 keywords
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Results
Found 58 publication records. Showing 58 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
70 | Robert N. Blair, Jacques Benkoski |
How Do You Select A High Quality EDA Tool Flow?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 17-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
60 | James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu |
A new efficient EDA tool design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 408-430, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Net Framework, C?, ESys.Net, attribute programming, embedded systems, SoC, VHDL, SystemC, modeling and simulation, CoDesign |
53 | Christos P. Sotiriou |
Implementing asynchronous circuits using a conventional EDA tool-flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 415-418, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
tool-flow, asynchronous, EDA |
47 | Giora Ben-Yaacov, Pramod Suratkar, Marsha Holliday, Karen Bartleson |
Advancing Quality of EDA Software (invited). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 81-86, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Amir A. Khwaja |
Enhancing extensibility of the design rule checker of an EDA tool by object-oriented modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 21st International Computer Software and Applications Conference (COMPSAC '97), 11-15 August 1997, Washington, DC, USA, pp. 104-108, 1997, IEEE Computer Society, 0-8186-8105-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
design rule checker, design rule checking systems, electronic design automation tools, semiconductor technology, DRC systems, DRC module, IC package design tool, object oriented modeling technique, abstraction, inheritance, extensibility, object oriented modeling, encapsulation, circuit CAD, dynamic binding, EDA tool |
42 | Lech Józwiak, Alexander Douglas |
Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 1123-1130, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
re-configurable computing, heterogeneous pipelined accelerators, hardware synthesis, EDA-tool |
33 | Walid Ibrahim |
A Novel EDA Tool for VLSI Test Vectors Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 421-434, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Test vectors selection, Genetic algorithms, Verification, VLSI, EDA tools |
32 | Richard Goldman, Karen Bartleson |
Tool Interoperability is Key to Improved Design Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 407-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Gary Smith 0001 |
A new era for CAD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 101, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Michaela Guiney, Eric Leavitt |
An introduction to OpenAccess: an open source data model and API for IC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 434-436, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Vijay Pitchumani |
Embedded tutorial I: design for manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore |
Analog intellectual property: now? Or never? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 181-182, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Mark C. Johnson |
igital Design Education Infrastructure Using Multiple EDA Tool Vendors and Multiple Modes of Tool Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2001 International Conference on Microelectronics Systems Education, MSE 2001, Las Vegas, NV, USA, July 17-18, 2001, pp. 81-82, 2001, IEEE Computer Society, 0-7695-1156-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Pinhong Chen, Kurt Keutzer, Desmond Kirkpatrick |
Scripting for EDA Tools: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 87-93, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Lionel Bening, Harry Foster |
Optimizing Multiple EDA Tools within the ASIC Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 18(4), pp. 46-55, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi |
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 329-334, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ODYSSEY, embedded systems, ASIP, JPEG |
21 | Pingakshya Goswami, Dinesh Bhatia |
Application of Machine Learning in FPGA EDA Tool Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 109564-109580, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Khader Mohammad, Nirmeen Al-Sheikh |
Efficient Implementation of a 4x4 Enhanced Pipeline Multiplier Using Electric EDA Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2023, Abu Dhabi, United Arab Emirates, December 17-20, 2023, pp. 131-136, 2023, IEEE, 979-8-3503-8082-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim |
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-6, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Florian Klemme, Sami Salamin, Hussam Amrouch |
Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-6, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Hwapyong Kim, Taewhan Kim |
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023, pp. 321-326, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Johannes Bastl, Zhihong Lei, Jonas Meier, Ralf Wunderlich, Stefan Heinen |
A Design Flow and EDA-Tool for an Automated Implementation of ASIC Configuration Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2022, Villasimius, Italy, June 12-15, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-6703-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Pere Millán-Martínez, Ramon Oller |
A Graphical EDA Tool with ggplot2: brinton. ![Search on Bibsonomy](Pics/bibsonomy.png) |
R J. ![In: R J. 12(2), pp. 311, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Jingsong Chen, Jian Kuang 0001, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young |
PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, pp. 17:1-17:8, 2020, IEEE. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Munish Jassi, Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 23(3), pp. 40:1-40:26, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi |
Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IVSW ![In: 3rd IEEE International Verification and Security Workshop, IVSW 2018, Costa Brava, Spain, July 2-4, 2018, pp. 74-79, 2018, IEEE, 978-1-5386-6544-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Antti Kamppi, Esko Pekkarinen, Janne Virtanen, Joni-Matti Määttä, Juho Järvinen, Lauri Matilainen, Mikko Teuho, Timo D. Hämäläinen |
Kactus2: A graphical EDA tool built on the IP-XACT standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Open Source Softw. ![In: J. Open Source Softw. 2(13), pp. 151, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Y. Q. de Aguiar, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis |
Permanent and single event transient faults reliability evaluation EDA tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 64, pp. 63-67, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Minas Dasygenis, Ioannis Petrousov |
A networking EDA tool for multi-vector multiplication IP circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1-2, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Giannis Petrousov, Minas Dasygenis |
A unique network EDA tool to create optimized ad hoc binary to residue number system converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014, pp. 1-8, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Minas Dasygenis |
A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2014, Santorini, Greece, May 6-8, 2014, pp. 1-2, 2014, IEEE, 978-1-4799-4972-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Yogesh Dilip Save, Rajalekshmi Rakhi, N. D. Shambhulingayya, Ambikeshwar Srivastava, Manas Ranjan Das, Saket Choudhary, Kannan M. Moudgalya |
Oscad: An open source EDA tool for circuit design, simulation, analysis and PCB design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, UAE, December 8-11, 2013, pp. 851-854, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Walid Ibrahim, Valeriu Beiu, Azam Beg |
GREDA: A Fast and More Accurate Gate Reliability EDA Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4), pp. 509-521, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Behnam Ghavami, Hossein Pedram, Mehrdad Najibi |
An EDA tool for implementation of low power and secure crypto-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 35(2), pp. 244-257, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Walid Ibrahim, Valeriu Beiu |
A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 276-284, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
nano-circuits, Reliability, Bayesian networks, EDA tools |
21 | Charles C. Chiang, Subarna Sinha |
The road to 3D EDA tool readiness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 429-436, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Benjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann |
4.25 Gb/s laser driver: design challenges and EDA tool limitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 863-866, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
electrical to optical interface, laser diode, laser driver |
21 | Jayanta Mukherjee 0002, Jason Parry, WenHua Dai, Patrick Roblin, Steven B. Bibyk, Jongsoo Lee |
RFIC Loadpull Simulations Implementing Best Practice RF and Mixed-Signal Design using an Integrated Agilent and Cadence EDA tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 76-77, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Rick Miller |
VHDL-based EDA Tool Implementation with Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 440-445, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Hardware/Software CoSynthesis, Java, VHDL |
21 | Luca Benini, Alessandro Bogliolo, Giovanni De Micheli |
Distributed EDA Tool Integration: The PPP Paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 448-453, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
sampling, processor simulation |
20 | Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian |
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 179-184, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
built-in self-test, embedded cores, EDA tools |
12 | Valeriy Sukharev, Ara Markosian, Armen Kteyan, Levon Manukyan, Nikolay Khachatryan, Jun-Ho Choy, Hasmik Lazaryan, Henrik Hovsepyan, Seiji Onoue, Takuo Kikuchi, Tetsuya Kamigaki |
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 156-161, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Aleksander Slusarczyk, Lech Józwiak |
Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 87-92, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
Intel® atomTM processor core made FPGA-synthesizable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 209-218, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
11 | Matt Nowak, Jose Corleto, Christopher Chun, Riko Radojcic |
Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 593, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
design technology integration, design exploration, pathfinding |
11 | Shuming Chen, Xiangyuan Liu |
A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 75-82, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
differential-signaling, insertion methodology, on-chip interconnects, low-swing |
11 | Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka |
A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, 25-28 June 2007, Edinburgh, UK, Proceedings, pp. 256-265, 2007, IEEE Computer Society, 0-7695-2855-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Vijay K. Madisetti |
Electronic System, Platform, and Package Codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(3), pp. 220-233, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
System-Level Design Automation, Electronic Packaging, System-on-Chip, Platform-Based Design, System-in-Package, System-on-Package |
11 | Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu |
Automatic Generation of Programmable Parallel CRC & Scrambler Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 286-291, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Masaya Yoshikawa, Hidekazu Terai |
Performance driven placement technique based on collaboration of software and hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2005, 2-4 September 2005, Edinburgh, UK, pp. 1570-1575, 2005, IEEE, 0-7803-9363-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Masaya Yoshikawa, Hidekazu Terai |
A Hierarchical Parallel Placement Technique based on Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA ![In: Proceedings of the Fifth International Conference on Intelligent Systems Design and Applications (ISDA 2005), 8-10 September 2005, Wroclaw, Poland, pp. 302-307, 2005, IEEE Computer Society, 0-7695-2286-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Yeshwant Kolla, Yong-Bin Kim, John Carter |
A novel 32-bit scalable multiplier architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 241-244, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CMOS VLSI, architecture, multiplier |
11 | Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi |
54x54-bit radix-4 multiplier based on modified booth algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 233-236, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
compressor, adder, multiplier, booth encoder, wallace tree |
11 | Ming-Hsiu Lai, Ming-Feng Yu, Sau-Gee Chen |
An efficient modified Phong shading algorithm & its low-complexity realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 201-204, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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11 | Adil Koukab, Catherine Dehollain, Michel J. Declercq |
HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 767-770, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
mixed-signal noise, supply noise, noise, numerical analysis, boundary-element-method, substrate noise, switching circuits, substrate coupling |
11 | Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun-Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee |
Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 404-408, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Decision feedback equalizer, reusable VLSI implementation, FIR filter, QAM |
11 | Hilary J. Kahn, Andy Carpenter, Nigel A. Whitaker |
A Web-Based System for Assessing and Searching for Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 755, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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11 | Chris W. H. Strolenberg |
Stay Away from Minimum Design-Rule Values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 71-72, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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