Search results for "EDAC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
103	Dariusz Badura, Andrzej Hlawiczka	Low Cost Bist for Edac Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	CBIST, EDAC, error aliasing, fault coverage, self-test
72	Avijit Dutta, Abhijit Jas	Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.	ISQED	2008	DBLP DOI BibTeX RDF	EDAC, adhoc code, customizable codes, ECC
54	Robert Werner (eds.)	EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
54	Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto	From Behavioral Description to Systolic Array Based Architectures.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Sybille Hellebrand, Hans-Joachim Wunderlich	Synthesis of Self-Testable Controllers.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Rob van Dongen, Vincent Rikkink	Advanced Analog Circuit Design on a Digital Sea-of-Gates Array.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Yosinori Watanabe, Robert K. Brayton	State Minimization of Pseudo Non-Deterministic FSM's.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess	On Design Rule Correct Maze Routing.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Vincent Moser, Pascal Nussbaum, Hans Peter Amann, Luc Astier, Fausto Pellandini	A Graphical Approach to Analogue Behavioural Modelling.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Michael Nicolaidis, Hakim Bederr	Efficient Implementations of Self-Checking Multiply and Divide Arrays.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel	Application of Simple Genetic Algorithms to Sequential Circuit Test Generation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Hannes C. Wittmann, Manfred Henftling	Efficient Path Identification for Delay Testing - Time and Space Optimization.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Kimon W. Michaels, Andrzej J. Strojwas	Variable Accuracy Device Modeling for Event-Driven Circuit Simulation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Sandip Parikh, Michael L. Bushnell, James Sienicki, Ganesh Ramakrishnan	Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Sandeep Bhatia, Niraj K. Jha	Genesis: A Behavioral Synthesis System for Hierarchical Testability.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Peter T. Breuer, Luis Sánchez Fernández 0001, Carlos Delgado Kloos	Clean formal semantics for VHDL.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Ben Chen, Michihiro Yamazaki, Masahiro Fujita	Bug Identification of a Real Chip Design by Symbolic Model Checking.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda	TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Jürgen Frößl, Thomas Kropf	A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	C. Safinia, Régis Leveugle, Gabriele Saucier	Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier	Taking Advantage of ASICs to Improve Dependability with Very Low Overheads.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Daniel Gajski, Frank Vahid, Sanjiv Narayan	A System-Design Methodology: Executable-Specification Refinement.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Abdessatar Abderrahman, Bozena Kaminska, Yvon Savaria	Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Manoj Sachdev	Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Sen-Pin Lin, Sandeep K. Gupta 0001, Melvin A. Breuer	A Low Cost BIST Methodology and Associated Novel Test Pattern Generator.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	M. Straube, Wolfgang Wilkes, Gunter Schlageter	HANDICAP - A System for Design Consulting.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel	Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Pierre Coulomb, François Pogodalla	PLFP256 A Pipelined Fourier Processor.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	D. Dumas, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Shan-Hsi Huang, Jan M. Rabaey	Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin 0001, Hugo De Man	A Generalized Signal Transition Graph Model for Specification of Complex Interfaces.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Martyn Edwards, John Forrest	A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	K. C. Koudakou	Software Implementation and Statistical Optimization of Some Electronic Component's Lifetime.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò	Modeling of Broken Connections Faults in CMOS ICs.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Bernd Wurth, Norbert Wehn	Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Koen Schoofs, Gert Goossens, Hugo De Man	Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Franco Fummi, Donatella Sciuto, Micaela Serra	A Functional Approach to Delay Faults Test Generation for Sequential Circuits.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man	Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Oliver F. Haberl, Thomas Kropf	Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang	Cell Height Driven Transistor Sizing in a Cell Based Module Design.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Chauchin Su	Random Testing of Interconnects in A Boundary Scan Environment.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Yih-Lang Li, Cheng-Wen Wu	Logic and Fault Simulation by Cellular Automata.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Thomas Johansson 0003, L. R. Virtanen, J. M. Gobbi	"Underground Capacitors" Very Efficient Decoupling for High Performance UHF Signal Processing ICs.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet	Logic Synthesis and Verification of the CPU and Caches of a Mainframe System.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska	Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Peter Zepter, Thorsten Grötker	Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Paolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas	System-Level Modeling and Verification: a Comprehensive Design Methodology.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Mani B. Srivastava, Miodrag Potkonjak	Transforming Linear Systems for Joint Latency and Throughout Optimization.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan	A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer	Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Tarek Ben Ismail, Kevin O'Brien, Ahmed Amine Jerraya	Interactive System-level Partitioning with PARTIF.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary	Multilevel Logic Synthesis of Very High Complexity Circuits.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Matti Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt	Boundary Scan Testing Combined with Power Supply Current Monitoring.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Loganath Ramachandran, Daniel Gajski, Viraphol Chaiyakul	An Algorithm for Array Variable Clustering.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira 0001, Thomas W. Williams	Fault Modeling and Defect Level Projections in Digital ICs.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre	Automatic Synthesis of BISTed Data Paths From High Level Specification.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Michel Robert, Patrick Gorria, Johel Mitéran, S. Turgis	Design of a Real Time Geometric Classifier.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Hua Xue, Chennian Di, Jochen A. G. Jess	Probability Analysis for CMOS Floating Gate Faults.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Bernard A. McCoy, Gabriel Robins	Non-Tree Routing.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Ad J. van de Goor, Yervant Zorian, Ivo Schanstra	Functional Tests for Ring-Address SRAM-type FIFOs.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu	A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Salman Ahmed, Peter Y. K. Cheung, Phil Collins	A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Eamonn Byrne, Oliver McCarthy, David Lucas, Brian Donnellan	An Overview of Analogue Optimisation Using "AD-OPT".	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Johannes Helbig, Peter Kelb	An OBDD-Representation of Statecharts.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Henrik Esbensen, Pinaki Mazumder	A Genetic Algorithm for the Steiner Problem in a Graph.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Sying-Jyan Wang	Synthesis of Sequential Machines with Reduced Testing Cost.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc	A Functionality Fault Model: Feasibility and Applications.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Roberto Sarmiento, Kamran Eshraghian	Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen	Synthesis of Application-Specific Multiprocessor Systems.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Eugeni Isern 0001, Joan Figueras	Test of Bridging Faults in Scan-based Sequential Circuits.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	A. Vacher, M. Benkhebbab, Alain Guyot, T. Rousseau, Ali Skaf	A VLSI Implementation of Parallel Fast Fourier Transform.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Richard McGowen, F. Joel Ferguson	A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Arno Kunzmann, Frank Böhland	Gate-Delay Fault Test with Conventional Scan-Design.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Richard Illman, D. J. Traynor	A Fragmented Register Architecture and Test Advisor for BIST.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Klaus Schneider 0001, Thomas Kropf, Ramayya Kumar	Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Mehmet Emin Dalkiliç, Vijay Pitchumani	Optimal Operation Scheduling Using Resource Lower Bound Estimations.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Lakshmikanth Ghatraju, Mostafa I. H. Abd-El-Barr, Carl McCrosky	High-Level Synthesis of Digital Circuits by Finding Fixpoints.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Mohamed Jamoussi, Bozena Kaminska	M-Testability: An Approach for Data-Path Testability Evaluation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Rosa Rodríguez-Montañés, Joan Figueras	Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin	A Synthesis Method for Mixed Synchronous / Asynchronous Behavior.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Anton Vuksic, Karl Fuchs	A New BIST Approach for Delay Fault Testing.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Andrea Boni, Giovanni Chiorboli, G. Franco, S. Mazzoleni, M. Ostacoli	Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Zhihua Wang, Stephen W. Director	An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani	Scheduling with Environmental Constraints based on Automata Representations.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Wuudiann Ke, Premachandran R. Menon	Synthesis of Delay-Verifiable Two-Level Circuits.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos	Design and Implementation of a High-Performance, Modular, Sorting Engine.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Bernhard Rohfleisch, Franc Brglez	Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan	Signal Transition Graph Transformations for Initializability.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Jiro Naganuma, Takeshi Ogura, Tamio Hoshino	High-Level Design Validation Using Algorithmic Debugging.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin	Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Bruno Rouzeyre, D. Dupont, Georges Sagnes	Component Selection, Scheduling and Control Schemes for High Level Synthesis.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Ralf Hahn, Rolf Krieger, Bernd Becker 0001	A Hierarchical Approach to Fault Collapsing.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Maurizio Damiani	Nondeterministic finite-state machines and sequential don't cares.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Champaka Ramachandran, Fadi J. Kurdahi	Incorporating the Controller Effects During Register Transfer Level Synthesis.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen, Won Yih Lin	Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Albrecht P. Stroele	Signature Analysis for Sequential Circuits with Reset.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Douglas M. Grant, Jef L. van Meerbergen, Paul E. R. Lippens	Optimization of Address Generator Hardware.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Wolfgang Vermeiren, Bernd Straube, Günter Elst	A Suggestion for Accelerating the Analog Fault Simulation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng	An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
54	Chih-Ang Chen, Sandeep K. Gupta 0001	BIST Test Pattern Generators for Stuck-Open and Delay Testing.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF