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Publication years (Num. hits)
1958-1968 (18) 1970-1974 (22) 1975-1976 (20) 1977-1979 (24) 1980-1981 (17) 1982-1984 (26) 1985 (25) 1986 (18) 1987 (40) 1988 (72) 1989 (44) 1990 (51) 1991 (22) 1992 (34) 1993 (36) 1994 (179) 1995 (83) 1996 (81) 1997 (135) 1998 (147) 1999 (237) 2000 (353) 2001 (407) 2002 (482) 2003 (601) 2004 (998) 2005 (1217) 2006 (1448) 2007 (1503) 2008 (1455) 2009 (931) 2010 (136) 2011-2012 (17) 2013-2016 (15) 2017-2020 (30) 2021-2022 (18) 2023-2024 (9)
Publication types (Num. hits)
article(1309) data(2) incollection(88) inproceedings(9551) proceedings(1)
Venues (Conferences, Journals, ...)
EDAC-ETC-EUROASIC(126) HICSS(88) SAC(84) SIGMOD Conference(66) IROS(59) DAC(53) ICDAR(53) WWW(51) WSC(50) ACM Multimedia(47) ICDE(47) IEEE Trans. Pattern Anal. Mach...(47) ICRA(45) IPDPS(44) IEEE Trans. Comput. Aided Des....(43) DATE(42) More (+10 of total 2109)
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Results
Found 10951 publication records. Showing 10951 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
44Robert Werner (eds.) EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  BibTeX  RDF
44Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto From Behavioral Description to Systolic Array Based Architectures. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Sybille Hellebrand, Hans-Joachim Wunderlich Synthesis of Self-Testable Controllers. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Rob van Dongen, Vincent Rikkink Advanced Analog Circuit Design on a Digital Sea-of-Gates Array. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Yosinori Watanabe, Robert K. Brayton State Minimization of Pseudo Non-Deterministic FSM's. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess On Design Rule Correct Maze Routing. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Vincent Moser, Pascal Nussbaum, Hans Peter Amann, Luc Astier, Fausto Pellandini A Graphical Approach to Analogue Behavioural Modelling. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Michael Nicolaidis, Hakim Bederr Efficient Implementations of Self-Checking Multiply and Divide Arrays. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Hannes C. Wittmann, Manfred Henftling Efficient Path Identification for Delay Testing - Time and Space Optimization. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Kimon W. Michaels, Andrzej J. Strojwas Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Sandip Parikh, Michael L. Bushnell, James Sienicki, Ganesh Ramakrishnan Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Sandeep Bhatia, Niraj K. Jha Genesis: A Behavioral Synthesis System for Hierarchical Testability. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Peter T. Breuer, Luis Sánchez Fernández 0001, Carlos Delgado Kloos Clean formal semantics for VHDL. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Ben Chen, Michihiro Yamazaki, Masahiro Fujita Bug Identification of a Real Chip Design by Symbolic Model Checking. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Jürgen Frößl, Thomas Kropf A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44C. Safinia, Régis Leveugle, Gabriele Saucier Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Daniel Gajski, Frank Vahid, Sanjiv Narayan A System-Design Methodology: Executable-Specification Refinement. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Abdessatar Abderrahman, Bozena Kaminska, Yvon Savaria Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Manoj Sachdev Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Sen-Pin Lin, Sandeep K. Gupta 0001, Melvin A. Breuer A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44M. Straube, Wolfgang Wilkes, Gunter Schlageter HANDICAP - A System for Design Consulting. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Pierre Coulomb, François Pogodalla PLFP256 A Pipelined Fourier Processor. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44D. Dumas, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Shan-Hsi Huang, Jan M. Rabaey Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin 0001, Hugo De Man A Generalized Signal Transition Graph Model for Specification of Complex Interfaces. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Martyn Edwards, John Forrest A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44K. C. Koudakou Software Implementation and Statistical Optimization of Some Electronic Component's Lifetime. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò Modeling of Broken Connections Faults in CMOS ICs. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Bernd Wurth, Norbert Wehn Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Koen Schoofs, Gert Goossens, Hugo De Man Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Franco Fummi, Donatella Sciuto, Micaela Serra A Functional Approach to Delay Faults Test Generation for Sequential Circuits. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Oliver F. Haberl, Thomas Kropf Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang Cell Height Driven Transistor Sizing in a Cell Based Module Design. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Chauchin Su Random Testing of Interconnects in A Boundary Scan Environment. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Yih-Lang Li, Cheng-Wen Wu Logic and Fault Simulation by Cellular Automata. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Thomas Johansson 0003, L. R. Virtanen, J. M. Gobbi "Underground Capacitors" Very Efficient Decoupling for High Performance UHF Signal Processing ICs. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Peter Zepter, Thorsten Grötker Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Paolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas System-Level Modeling and Verification: a Comprehensive Design Methodology. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Mani B. Srivastava, Miodrag Potkonjak Transforming Linear Systems for Joint Latency and Throughout Optimization. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Tarek Ben Ismail, Kevin O'Brien, Ahmed Amine Jerraya Interactive System-level Partitioning with PARTIF. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary Multilevel Logic Synthesis of Very High Complexity Circuits. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Matti Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt Boundary Scan Testing Combined with Power Supply Current Monitoring. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Loganath Ramachandran, Daniel Gajski, Viraphol Chaiyakul An Algorithm for Array Variable Clustering. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira 0001, Thomas W. Williams Fault Modeling and Defect Level Projections in Digital ICs. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre Automatic Synthesis of BISTed Data Paths From High Level Specification. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Michel Robert, Patrick Gorria, Johel Mitéran, S. Turgis Design of a Real Time Geometric Classifier. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Hua Xue, Chennian Di, Jochen A. G. Jess Probability Analysis for CMOS Floating Gate Faults. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Bernard A. McCoy, Gabriel Robins Non-Tree Routing. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Ad J. van de Goor, Yervant Zorian, Ivo Schanstra Functional Tests for Ring-Address SRAM-type FIFOs. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Salman Ahmed, Peter Y. K. Cheung, Phil Collins A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Eamonn Byrne, Oliver McCarthy, David Lucas, Brian Donnellan An Overview of Analogue Optimisation Using "AD-OPT". Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Johannes Helbig, Peter Kelb An OBDD-Representation of Statecharts. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Henrik Esbensen, Pinaki Mazumder A Genetic Algorithm for the Steiner Problem in a Graph. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Sying-Jyan Wang Synthesis of Sequential Machines with Reduced Testing Cost. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc A Functionality Fault Model: Feasibility and Applications. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Roberto Sarmiento, Kamran Eshraghian Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen Synthesis of Application-Specific Multiprocessor Systems. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Eugeni Isern 0001, Joan Figueras Test of Bridging Faults in Scan-based Sequential Circuits. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44A. Vacher, M. Benkhebbab, Alain Guyot, T. Rousseau, Ali Skaf A VLSI Implementation of Parallel Fast Fourier Transform. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Richard McGowen, F. Joel Ferguson A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Arno Kunzmann, Frank Böhland Gate-Delay Fault Test with Conventional Scan-Design. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Richard Illman, D. J. Traynor A Fragmented Register Architecture and Test Advisor for BIST. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Klaus Schneider 0001, Thomas Kropf, Ramayya Kumar Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Mehmet Emin Dalkiliç, Vijay Pitchumani Optimal Operation Scheduling Using Resource Lower Bound Estimations. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Lakshmikanth Ghatraju, Mostafa I. H. Abd-El-Barr, Carl McCrosky High-Level Synthesis of Digital Circuits by Finding Fixpoints. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Mohamed Jamoussi, Bozena Kaminska M-Testability: An Approach for Data-Path Testability Evaluation. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Rosa Rodríguez-Montañés, Joan Figueras Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Anton Vuksic, Karl Fuchs A New BIST Approach for Delay Fault Testing. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Andrea Boni, Giovanni Chiorboli, G. Franco, S. Mazzoleni, M. Ostacoli Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Zhihua Wang, Stephen W. Director An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani Scheduling with Environmental Constraints based on Automata Representations. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Wuudiann Ke, Premachandran R. Menon Synthesis of Delay-Verifiable Two-Level Circuits. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos Design and Implementation of a High-Performance, Modular, Sorting Engine. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Bernhard Rohfleisch, Franc Brglez Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan Signal Transition Graph Transformations for Initializability. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Jiro Naganuma, Takeshi Ogura, Tamio Hoshino High-Level Design Validation Using Algorithmic Debugging. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Bruno Rouzeyre, D. Dupont, Georges Sagnes Component Selection, Scheduling and Control Schemes for High Level Synthesis. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Ralf Hahn, Rolf Krieger, Bernd Becker 0001 A Hierarchical Approach to Fault Collapsing. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Maurizio Damiani Nondeterministic finite-state machines and sequential don't cares. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Champaka Ramachandran, Fadi J. Kurdahi Incorporating the Controller Effects During Register Transfer Level Synthesis. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen, Won Yih Lin Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Albrecht P. Stroele Signature Analysis for Sequential Circuits with Reset. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Douglas M. Grant, Jef L. van Meerbergen, Paul E. R. Lippens Optimization of Address Generator Hardware. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Wolfgang Vermeiren, Bernd Straube, Günter Elst A Suggestion for Accelerating the Analog Fault Simulation. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Chih-Ang Chen, Sandeep K. Gupta 0001 BIST Test Pattern Generators for Stuck-Open and Delay Testing. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Bernd Becker 0001, Rolf Drechsler Testability of Circuits Derived from Functional Decision Diagrams. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
44Makoto Ikeda, Kunihiro Asada A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. Search on Bibsonomy EDAC-ETC-EUROASIC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
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