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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 29 occurrences of 25 keywords
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Results
Found 79 publication records. Showing 79 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
58 | Wen-Jong Fang, Allen C.-H. Wu |
Multiway FPGA partitioning by fully exploiting design hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(1), pp. 34-50, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis |
56 | Jason Cong, Kirill Minkovich |
Optimality Study of Logic Synthesis for LUT-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 230-239, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Navin Vemuri, Priyank Kalla, Russell Tessier |
BDD-based logic synthesis for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 501-525, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, decomposition, logic synthesis, BDD |
46 | Jason Cong, Kirill Minkovich |
Optimality study of logic synthesis for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 33-40, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table |
31 | Jason Cong, Chang Wu |
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 644-649, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang |
Logic synthesis for field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10), pp. 1280-1287, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
30 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
DDBDD: Delay-Driven BDD Synthesis for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), pp. 1203-1213, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
DDBDD: Delay-Driven BDD Synthesis for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 910-915, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 13-17, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
LUT-Based FPGA Technology Mapping, Area/Performance Trade-Off and Timing Driven FPGA Synthesis |
24 | Wen-Jong Fang, Allen C.-H. Wu |
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 518-521, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
20 | John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang |
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 780-785, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BCP, FPGA, reconfigurable, SAT solver, co-processor |
18 | Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil |
Parameterized Looped Schedules for Compact Representationof Execution Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 223-230, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Francisco-Javier Veredas, Jordi Carrabina |
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 666-673, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek |
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-6, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Christophe Desmouliers, Erdal Oruklu, Jafar Saniie |
FPGA-based design of a high-performance and modular video processing platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 393-398, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada |
Compact Spiking Neural Network Implementation in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 270-276, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | P. Subramanian, Jagonda Patil, Manish Kumar Saxena |
FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, IWCMC 2009, Leipzig, Germany, June 21-24, 2009, pp. 1355-1358, 2009, ACM, 978-1-60558-569-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating |
16 | Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro 0001, Sergio Bampi |
An improved synthesis method for low power hardwired FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 237-241, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA synthesis, parallel FIR filter, power-of-two, common subexpression elimination |
16 | Jason Cong, Yizhou Lin, Wangning Long |
SPFD-based global rewiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 77-84, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis |
16 | Kang Yi, Seong Yong Ohm |
A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 319-320, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Cell Matching, FPGA Technology Mapping, FPGA Synthesis |
16 | Wen-Jong Fang, Allen C.-H. Wu |
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 638-643, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Multiple-FPGA partitioning, multiple-FPGA synthesis, functional structuring and functional partitioning |
15 | Iyad Ouaiss, Ranga Vemuri |
Efficient Resource Arbitration in Reconfigurable Computing Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 560-566, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Chun Zhang, Yu Hu 0002, Lingli Wang, Lei He 0001, Jiarong Tong |
Building a faster boolean matcher using bloom filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 185-188, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
FPGA, SAT, bloom filter, boolean matching, re-synthesis |
14 | Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi |
A VHDL Generation Tool for Optimized Parallel FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 134-139, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Jirong Liao, Weng-Fai Wong, Tulika Mitra |
A Model for Hardware Realization of Kernel Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 334-344, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 392-400, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
12 | Xiaoyuan Wang, Zhiru Wu, Pengfei Zhou, Herbert Ho-Ching Iu, Sung-Mo Steve Kang 0001, Jason Kamran Eshraghian |
FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(9), pp. 3501-3511, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Federico Rossi 0003, Lorenzo Fiaschi, Marco Cococcioni, Sergio Saponara |
Design and FPGA Synthesis of BAN Processing Unit for Non-Archimedean Number Crunching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2022, Genoa, Italy, 26-27 September 2022., pp. 320-325, 2022, Springer, 978-3-031-30332-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Ompal, Vishnu Mohan Mishra, Adesh Kumar |
Zigbee Internode Communication and FPGA Synthesis Using Mesh, Star and Cluster Tree Topological Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 119(2), pp. 1321-1339, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
12 | Xiaoyuan Wang, Zhiru Wu, Pengfei Zhou, Herbert H. C. Iu, Jason Kamran Eshraghian, Sung Mo Kang 0001 |
FPGA Synthesis of Ternary Memristor-CMOS Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.10297, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
12 | Yann Herklotz, John Wickerson |
Finding and Understanding Bugs in FPGA Synthesis Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 23-25, 2020, pp. 277-287, 2020, ACM, 978-1-4503-7099-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
12 | Adesh Kumar, Gaurav Verma, Mukul Kumar Gupta, Mohammad Salauddin, B. Khaleelu Rehman, Deepak Kumar 0009 |
3D Multilayer Mesh NoC Communication and FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 106(4), pp. 1855-1873, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
12 | Ehsan Jokar, Hadis Abolfathi, Arash Ahmadi, Majid Ahmadi |
An Efficient Uniform-Segmented Neuron Model for Large-Scale Neuromorphic Circuit Design: Simulation and FPGA Synthesis Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6), pp. 2336-2349, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
12 | Archit Gajjar, Xiaokun Yang, Lei Wu, Hakduran Koc, Ishaq Unwala, Yunxiang Zhang 0001, Yi Feng |
An FPGA Synthesis of Face Detection Algorithm using HAAR Classifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACS ![In: Proceedings of the 2018 2nd International Conference on Algorithms, Computing and Systems, ICACS 2018, Beijing, China, July 27-29, 2018, pp. 133-137, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Hamid Soleimani, Emmanuel M. Drakakis |
A Compact Synchronous Cellular Model of Nonlinear Calcium Dynamics: Simulation and FPGA Synthesis Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 11(3), pp. 703-713, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
12 | Swathi T. Gurumani, Jacob Tolar, Yao Chen 0008, Yun Liang 0001, Kyle Rupnow, Deming Chen |
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014, pp. 21-24, 2014, IEEE Computer Society, 978-1-4799-5110-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Mohamed Azim Mohamed |
FPGA Synthesis of VHDL OFDM System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 70(4), pp. 1885-1909, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
12 | Matthew Milford, John McAllister |
Automatic FPGA synthesis of memory intensive C-based kernels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012, pp. 136-143, 2012, IEEE, 978-1-4673-2295-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
12 | Arkadiusz Bukowiec, Piotr Mroz |
An FPGA synthesis of the distributed control systems designed with Petri nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NESEA ![In: 3rd IEEE International Conference on Networked Embedded Systems for Every Application, NESEA 2013, Liverpool, United Kingdom, December 13-14, 2012, pp. 1-6, 2012, IEEE Computer Society, 978-1-4673-4721-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
12 | Mike Hutton, Vaughn Betz |
FPGA Synthesis and Physical Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Systems Design and Verification ![In: Embedded Systems Design and Verification - Volume 1 of the Embedded Systems Handbook, pp. 17, 2009, CRC Press, 978-1-4398-0755-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus, Konstantin Tarletski |
FSM decomposition with application to FPGA synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CompSysTech ![In: Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, CompSysTech 2009, Rousse, Bulgaria, June 18-19, 2009, pp. 74, 2009, ACM, 978-1-60558-986-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Yue Zhuo, Hao Li, Qiang Zhou 0001, Yici Cai, Xianlong Hong |
New timing and routability driven placement algorithms for FPGA synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 570-575, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
congestion driven placement, physical synthesis, timing driven placement, net weight |
12 | Yue Zhuo, Hao Li, Saraju P. Mohanty |
A Congestion Driven Placement Algorithm for FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius |
Highly Automated FPGA Synthesis of Application-Specific Protocol Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 269-274, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Lech Józwiak, Artur Chojnacki |
Effective and efficient FPGA synthesis through general functional decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 49(4-6), pp. 247-265, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Seong Yong Ohm, Ki-Yeol Ryu, Kang Yi |
Lower Bound Estimation on the Numbers of LUT Blocks and Micro-Registers for Time-Mulitplexed FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Engineering of Reconfigurable Systems and Algorithms ![In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23 - 26, 2003, Las Vegas, Nevada, USA, pp. 321-324, 2003, CSREA Press. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
12 | Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo |
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 47-58, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Christoph Scholl 0001 |
Functional decomposition with applications to FPGA synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2001 |
RDF |
|
12 | Lech Józwiak, Artur Chojnacki |
Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 30-37, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Jian Qiao, Makoto Ikeda, Kunihiro Asada |
Finding an optimal functional decomposition for LUT-based FPGA synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 225-230, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
12 | Jian Qiao, Makoto Ikeda, Kunihiro Asada |
Optimum Functional Decomposition for LUT-Based FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 555-564, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
12 | John McCluskey |
Practical Applications of Recursive VHDL Components in FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999, pp. 252, 1999, ACM, 1-58113-088-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu |
A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 351-354, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Per Lindgren, Rolf Drechsler, Bernd Becker 0001 |
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 28th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1998, Fukuoka, Japan, May 27-29, 1998, Proceedings, pp. 95-101, 1998, IEEE Computer Society, 0-8186-8371-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
12 | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang |
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 712-717, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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12 | Jason Cong, Yean-Yow Hwang |
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997, pp. 35-42, 1997, ACM, 0-89791-801-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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12 | Roger F. Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring |
FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 155-164, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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12 | Kuo-Rueih Ricky Pan, Massoud Pedram |
FPGA synthesis for minimum area, delay and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996, pp. 603, 1996, IEEE Computer Society, 0-8186-7423-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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12 | Christoph Scholl 0001, Paul Molitor |
Communication based FPGA synthesis for multi-output Boolean functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995, 1995, ACM, 0-89791-766-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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12 | Ted Stanion, Carl Sechen |
A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 60-64, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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12 | Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram |
FPGA Synthesis Using Function Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 30-35, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Ricardo P. Jacobi, Anne-Marie Trullemans |
A new logic minimization method for multiplexor-based FPGA synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993, pp. 312-317, 1993, IEEE Computer Society, 0-8186-4350-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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12 | Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula |
BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 642-647, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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11 | Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer |
Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 405-408, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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11 | Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi |
A High Performance Parallel FIR Filters Generation Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece, pp. 216-222, 2006, IEEE Computer Society, 0-7695-2580-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton |
Topologically constrained logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 679-686, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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8 | Gang Zhou, Li Li 0027, Harald Michalik |
Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 671-674, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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8 | Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga |
Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1248-1251, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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8 | Tirath Ramdas, Gregory K. Egan, David Abramson 0001, Kim K. Baldridge |
Run-time thread sorting to expose data-level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 55-60, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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8 | Sin Man Cheang, Kin-Hong Lee, Kwong-Sak Leung |
Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 11(4), pp. 503-520, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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8 | Wei Li 0131, Zibin Dai, Tao Chen 0047, Tao Meng, Xuan S. Yang |
Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 7th International Symposium, APPT 2007, Guangzhou, China, November 22-23, 2007, Proceedings, pp. 50-59, 2007, Springer, 978-3-540-76836-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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8 | Marcelo Schiavon Porto, Luciano Volcan Agostini, Leandro Rosa, Altamiro Amadeu Susin, Sergio Bampi |
High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PSIVT ![In: Advances in Image and Video Technology, Second Pacific Rim Symposium, PSIVT 2007, Santiago, Chile, December 17-19, 2007, Proceedings, pp. 36-47, 2007, Springer, 978-3-540-77128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Motion estimation, hardware architecture, FPGA design |
8 | Mark G. Arnold |
A RISC Processor with Redundant LNS Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 475-482, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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8 | T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani |
SEU Mitigation Techniques for Microprocessor Control Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Sixth European Dependable Computing Conference, EDCC 2006, Coimbra, Portugal, 18-20 October 2006, pp. 77-86, 2006, IEEE Computer Society, 0-7695-2648-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Raymond R. Hoare, Zhu Ding, Alex K. Jones |
Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 94, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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8 | Uwe Meyer-Bäse, Jiajia Chen 0002, Chip-Hong Chang, Andrew G. Dempster |
A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1555-1558, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Massimo Baleani, Massimo Conti, Alberto Ferrari, Valerio Frascolla, Alberto L. Sangiovanni-Vincentelli |
An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 677-686, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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8 | Jim Armstrong, Amy Bell, Gail Gray |
An Intra-Disciplinary Capstone Project in Digital Filter Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2001 International Conference on Microelectronics Systems Education, MSE 2001, Las Vegas, NV, USA, July 17-18, 2001, pp. 52-53, 2001, IEEE Computer Society, 0-7695-1156-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
8 | Jason Cong, Kenneth Yan |
Synthesis for FPGAs with embedded memory blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 75-82, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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