|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 197 occurrences of 123 keywords
|
|
|
Results
Found 450 publication records. Showing 450 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
140 | Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet |
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 430-441, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
asynchronous/synchronous operation, VLSI, interfaces, GALS |
114 | Xin Jia, Ranga Vemuri |
Using GALS architecture to reduce the impact of long wire delay on FPGA performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1260-1263, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
100 | Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen |
Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 83-88, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
87 | Michael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens |
Guest Editors' Introduction: GALS Design and Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 414-416, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
design, synchronous, validation, asynchronous |
87 | Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner |
GALS at ETH Zurich: Success or Failure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 150-159, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
87 | Milos Krstic, Eckhard Grass, Christian Stahl |
Request-Driven GALS Technique for Wireless Communication System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 76-85, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
81 | Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi |
Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 269, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
81 | Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi |
Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 63-69, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
79 | Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux |
A Survey and Taxonomy of GALS Design Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 418-428, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
globally asynchronous, locally synchronous (GALS), clock domains, pausible clocks, loosely synchronous, synchronization, asynchronous |
79 | Matthew W. Heath, Wayne P. Burleson, Ian G. Harris |
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(12), pp. 1532-1546, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test, debug, SoC, nondeterminism, GALS, globally asynchronous locally synchronous |
74 | Eckhard Grass, Frank Winkler 0001, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz |
Enhanced GALS Techniques for Datapath Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 581-590, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
73 | Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi |
A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 296-301, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
on-chip clock generation, FPGA, GALS |
73 | Diana Marculescu, Emil Talpes |
Variability and energy awareness: a microarchitecture-level perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 11-16, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
GALS design, power consumption, variability |
73 | Alain Girault, Clément Ménier |
Automatic Production of Globally Asynchronous Locally Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Embedded Software, Second International Conference, EMSOFT 2002, Grenoble, France, October 7-9, 2002, Proceedings, pp. 266-281, 2002, Springer, 3-540-44307-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Globally synchronous-locally asynchronous (GALS), asynchronous communications, hardware/software codesign, distributed architectures, synchronous circuits, automatic distribution |
67 | Anoop Iyer, Diana Marculescu |
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 158-168, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
66 | Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet |
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 129-138, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pausable clock, Vdd Hopping, Network-on-Chip, power, DVFS, GALS |
60 | Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou |
High Rate Data Synchronization in GALS SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(10), pp. 1063-1074, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Sandeep K. Shukla, Michael Theobald |
Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 28(2), pp. 91-92, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen |
Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Milos Krstic, Eckhard Grass |
BIST Technique for GALS Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 10-16, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
59 | Avinash Malik, Zoran A. Salcic, Alain Girault, Adam Walker, Sung Chul Lee |
A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES 2009, Madrid, Spain, September 23-25, 2009, pp. 120-129, 2009, ACM, 978-1-60558-732-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
synchronous and asynchronous concurrency, multiprocessor, GALS, reactivity |
59 | Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili |
Optimal partitioning of globally asychronous locally synchronous processor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 7-12, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLSI, partitioning, power optimization, GALS |
54 | Zhiyi Yu, Bevan M. Baas |
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 378-383, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Matthew W. Heath, Wayne P. Burleson, Ian G. Harris |
Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 410-415, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 181-189, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang |
A GALS Infrastructure for a Massively Parallel Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 454-463, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling |
52 | Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley |
GALS SoC interconnect bus for wireless sensor network processor platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 132-137, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS |
52 | Supratik Chakraborty, Joycee Mekie, Dinesh K. Sharma |
Reasoning about synchronization in GALS systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 28(2), pp. 153-169, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Symbolic timing analysis, GALS systems, Multi-clocked systems, Symbolic delay constraints, Synchronization constraints, Sequencing constraints |
52 | Grigorios Magklis, Pedro Chaparro, José González 0002, Antonio González 0001 |
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 49-54, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MCD, energy efficiency, DVS, microarchitecture, GALS |
47 | Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe |
Towards Performance Prediction of Compositional Models in Industrial GALS Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 204-218, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | Hubert Garavel, Damien Thivolle |
Verification of GALS Systems by Combining Synchronous Languages and Process Calculi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 16th International SPIN Workshop, Grenoble, France, June 26-28, 2009. Proceedings, pp. 241-260, 2009, Springer, 978-3-642-02651-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades |
Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(6), pp. 572-580, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya |
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 797-802, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura |
Dynamic Instruction Cascading on GALS Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 30-39, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Jerome Quartana, Laurent Fesquet, Marc Renaudin |
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 195-207, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Christian Stahl, Wolfgang Reisig, Milos Krstic |
Hazard Detection in a GALS Wrapper: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 234-243, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | S. Ramesh, Sampada Sonalkar, Vijay D'Silva, Naveen Chandra, B. Vijayalakshmi |
A Toolset for Modelling and Verification of GALS Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings, pp. 506-509, 2004, Springer, 3-540-22342-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Sonia López, Oscar Garnica, José Manuel Colmenar |
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 623-632, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott |
Dynamically Trading Frequency for Complexity in a GALS Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 157-168, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Milos Krstic, Eckhard Grass |
New GALS Technique for Datapath Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 161-170, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Jean-Michel Chabloz, Ahmed Hemani |
Distributed DVFS using rationally-related frequencies and discrete voltage levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 247-252, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
GRLS, DVFS, GALS |
46 | Tomi Westerlund, Juha Plosila |
Time Aware Modelling and Analysis of Multiclocked VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 8th International Conference on Formal Engineering Methods, ICFEM 2006, Macao, China, November 1-3, 2006, Proceedings, pp. 737-756, 2006, Springer, 3-540-47460-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Timed Action Systems, formal methods, time, GALS |
46 | Venkata Syam P. Rapaka, Diana Marculescu |
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 372-377, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
issue window design, mixed-clock circuits, GALS |
46 | Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage |
Clock Synchronization through Handshake Signalling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 59-68, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
GALS systems, pausible clocks, asynchronous crossbar/bus, processor/memory architectures |
40 | Avinash Malik, Zoran A. Salcic, Partha S. Roop |
SystemJ compilation using the tandem virtual machine approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 34:1-34:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SystemJ, compilation, virtual machines, System-level design, esterel |
40 | Kwang-Ting (Tim) Cheng |
Combining synchronous and asynchronous timing schemes for high-performance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 412, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-performance systems, synchronous, asynchronous, DAC, ITC |
40 | Daniele Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra |
Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 519-526, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes 0001, Ney Calazans |
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 541-546, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Milos Krstic, Eckhard Grass |
GALSification of IEEE 802.11a Baseband Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 258-267, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Chia-Chih Kuo, Kuan-Yu Chen |
GALs: 基於對抗式學習之整列式摘要法 (GALs: A GAN-based Listwise Summarizer). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ROCLING ![In: Proceedings of the 31st Conference on Computational Linguistics and Speech Processing, ROCLING 2019, New Taipei City, Taiwan, October 3-5, 2019., pp. 15-24, 2019, The Association for Computational Linguistics and Chinese Language Processing (ACLCLP). The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
40 | Lina Marsso |
On Model-based Testing of GALS Systems. (Etude de génération de tests à partir d'un modèle pour les systèmes GALS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
40 | Muhammad Nadeem, HeeJong Park 0001, Zhenmin Li, Morteza Biglari-Abhari, Zoran Salcic |
GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2013 - 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings, pp. 147-158, 2013, Springer, 978-3-642-36423-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
40 | Wei-Tsun Sun, Zoran Salcic |
GALS-Designer: A design framework for GALS software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 16(4), pp. 39:1-39:24, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
40 | Muhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic |
GALS-JOP: A Java Embedded Processor for GALS Reactive Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASC ![In: IEEE Ninth International Conference on Dependable, Autonomic and Secure Computing, DASC 2011, 12-14 December 2011, Sydney, Australia, pp. 292-299, 2011, IEEE Computer Society, 978-0-7695-4612-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
40 | Nicolas Coste |
Towards Performance Prediction of Compositional Models in GALS Designs. (Vers la prédiction de performance de modèles compositionnels dans les architectures GALS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
40 | Yue Ma 0004 |
Compositional modeling of globally asynchronous locally synchronous (GALS) architectures in a polychronous model of compotation. (Modélisation compositionnelle d'architectures globalement asynchrones - localement synchrones (GALS) dans un modèle de calcul polychrone). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
39 | Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres |
A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 28(5), pp. 62-71, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
cryptography attacks, DPA, asynchronous, SCA, GALS, design and test, DEMA |
39 | Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner |
A switch architecture and signal synchronization for GALS system-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 210-215, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
NoC switch, clock stretching, synchronization, GALS |
33 | Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla |
A Trace-Based Framework for Verifiable GALS Composition of IPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1176-1186, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz |
Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 14-17, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Prashant Dubey, Akhil Garg 0001, Sravan Kumar Bhaskarani |
GALS Based Shared Test Architecture for Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 157-160, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu |
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 110-115, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Abbas Sheibanyrad, Alain Greiner |
Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 191-202, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Edith Beigné, Pascal Vivet |
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 172-183, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan |
Interface Design for Rationally Clocked GALS Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 160-171, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Xin Jia, Ranga Vemuri |
Studying a GALS FPGA architecture using a parameterized automatic design flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 688-693, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Yongkang Zhu, David H. Albonesi |
Synergistic temperature and energy management in GALS processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 55-60, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic temperature management (DTM), dynamic voltage scaling (DVS) |
33 | Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy 0001 |
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 752-766, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Asynchronous/synchronous operations, fault tolerance, energy-aware systems, algorithms implemented in hardware |
33 | Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy 0001 |
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 358-363, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou |
Data Synchronization Issues in GALS SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 170-180, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas |
Hiding Synchronization Delays in a GALS Processor Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 159-169, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma |
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 559-564, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson 0001 |
Point to Point GALS Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 69-75, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas |
Architecture and Evaluation of an Asynchronous Array of Simple Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 243-259, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous |
32 | Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har |
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 46(2-3), pp. 133-151, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS |
32 | Dumitru Potop-Butucaru, Benoît Caillaud, Albert Benveniste |
Concurrency in Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 28(2), pp. 111-130, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Globally asynchronous locally synchronous (GALS), Concurrency, Synchronous, Distribution, Desynchronization, Trace theory |
32 | Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli |
A Framework for Modeling the Distributed Deployment of Synchronous Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 28(2), pp. 93-110, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Distributed systems, GALS, Desynchronization, Latency-insensitive design |
32 | Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har |
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 152-155, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous on-chip bus, in-order completion, multiple issue, out-of-order completion, SoC, GALS |
27 | Sanghamitra Bandyopadhyay, Sriparna Saha 0001 |
A New Principal Axis Based Line Symmetry Measurement and Its Application to Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (2) ![In: Advances in Neuro-Information Processing, 15th International Conference, ICONIP 2008, Auckland, New Zealand, November 25-28, 2008, Revised Selected Papers, Part II, pp. 543-550, 2008, Springer, 978-3-642-03039-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Xin Wang, Tapani Ahonen, Jari Nurmi |
Applying CDMA Technique to Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1091-1100, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet |
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 295-306, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu |
Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 869-872, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares |
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 136-150, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha |
An Efficient Clocking Scheme for On-Chip Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 119-122, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Andrew Royal, Peter Y. K. Cheung |
Globally Asynchronous Locally Synchronous FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 355-364, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Anoop Iyer, Diana Marculescu |
Power efficiency of voltage scaling in multiple clock, multiple voltage cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 379-386, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Weiyi Zhang 0003, Zoran Salcic, Avinash Malik |
Designing, Modeling and Analysis of GALS Software Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 49(8), pp. 3989-4003, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Hitesh Ahuja, Rajkumar Kubendran |
High-resolution Extreme-throughput Event-based Cameras using GALS Data-scanning Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONS ![In: Proceedings of the 2023 International Conference on Neuromorphic Systems, ICONS 2023, Santa Fe, NM, USA, August 1-3, 2023, pp. 12:1-12:6, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Dalta Imam Maulana, Wanyeong Jung |
An Energy-Efficient Delay Insensitive Asynchronous Interface for Globally Asynchronous Locally Synchronous (GALS) System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Alberto Abelló, Panos Vassiliadis, Oscar Romero 0001, Robert Wrembel, Francesca Bugiotti, Johann Gamper, Genoveva Vargas-Solar, Ester Zumpano (eds.) |
New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![Springer, 978-3-031-42940-8 The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Alexandros Karakasidis 0001, Georgia Koloniari |
Exploring Biases for Privacy-Preserving Phonetic Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 95-105, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Mariella Bonomo, Francesco Ippolito, Salvatore Morfea |
A Knowledge Graph to Analyze Clinical Patient Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 477-484, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Sandro Bimonte, Patrick Marcel, Stefano Rizzi |
Be High on Emotion: Coping with Emotions and Emotional Intelligence when Querying Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 82-91, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Elodie Escriva, Emmanuel Doumard, Jean-Baptiste Excoffier, Julien Aligon, Paul Monsarrat, Chantal Soulé-Dupuy |
Data Exploration Based on Local Attribution Explanation: A Medical Use Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 315-323, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Heloisa Fernanda Rocha, Lorena Silva Nascimento, Leonardo Camargo, Mauricio Noernberg, Carmem S. Hara |
Labeling Portuguese Man-of-War Posts Collected from Instagram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 369-381, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Hacene Belhadef, Hala Benchiheb, Lynda Lebdjiri |
Exploring the Capabilities and Limitations of VQC and QSVC for Sentiment Analysis on Real-World and Synthetic Datasets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 415-424, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Quim Motger, Xavier Franch, Jordi Marco |
Mobile Feature-Oriented Knowledge Base Generation Using Knowledge Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 269-279, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Yousra Bouakba, Hacene Belhadef |
Ensemble Learning Based Quantum Text Classifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 407-414, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Joakim Lindén, Håkan Forsberg, Masoud Daneshtalab, Ingemar Söderquist |
Evaluating the Robustness of ML Models to Out-of-Distribution Data Through Similarity Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 348-359, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Søren Kejser Jensen, Christian Thomsen 0001 |
Holistic Analytics of Sensor Data from Renewable Energy Sources: A Vision Paper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADBIS (Short Papers) ![In: New Trends in Database and Information Systems - ADBIS 2023 Short Papers, Doctoral Consortium and Workshops: AIDMA, DOING, K-Gals, MADEISD, PeRS, Barcelona, Spain, September 4-7, 2023, Proceedings, pp. 360-366, 2023, Springer, 978-3-031-42940-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 450 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ 5][ >>] |
|